Obviously the brains of this project are all inside the FPGA and are unlikely to be easily reproducible. I'm using a hacked up board I developed for a client almost a decade ago. It's not available commercially but it was something I had laying around and decided to put it to use. The FPGA essentially consists of three main areas - the discrete logic that decodes the 1553 bit stream, the FIFO and time stamping and the Nios CPU core. All the time sensitive operations are written in VHDL and the non time-critical sections are written in C.

The 1553 analog front end consists of a transformer coupler followed by a pair of high speed comparators. There are two digital outputs, one each for the positive and negative sides of the bus. These inputs are fed directly into the FPGA. The receiver block decodes the bit stream and writes the data into a FIFO along with a timestamp. Once the buffer is full, the Nios CPU takes control, reading the data out of the FIFO and formatting it into ASCII suitable for display on a PC. It streams the data via a UART to an external CH340G . The baud rate is not critical since it's not operating in real time. The FPGA I'm using has enough internal RAM to buffer about 16000 1553 packets.

The displayed data consists of an incremental timestamp and a delta timestamp showing the time since the previous packet. A resolution of 0.1us is used for both. Each command or data packet is denoted by a C or D respectively. Where a command/status packet is detected, the remote terminal (RT) address is shown.

This is just a proof-of-concept prototype. The eventual goal is to shrink it all onto one board, using a smaller/cheaper FPGA, ideally plugging into something like a Raspberry Pi or Arduino.