Ring Oscillators: Fairchild DTL 949

Three-inverter ring oscillator with fourth gate as a buffer

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Built a three-inverter ring oscillator on solderless breadboard using Fairchild DTL 949 NAND gate from 1968; unused input are tied to Vcc and output is buffered with the remaining NAND gate. Operates around 10.3MHz.

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Dana Myers wrote 11/11/2022 at 22:02 point

Minimum and maxumum propagation delays are specified in datasheets as design limits across the complete temperature and voltage range of operation, and usually with a high load. Typical propagation delays tend to be much less and thus you see this kind of variation.

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Ken Yap wrote 11/11/2022 at 21:28 point

Read this a while back and found it again from a search. Wikipedia says the frequency for a 3-gate ring should be the reciprocal of 6 " gate delay. 10 MHz mplies a gate delay of 16 ns. According to the datasheet I have the propagation delay is 25 ns. But I expect discrepancy as DTL rise and fall times are asymmetric; the Wiki example uses CMOS gates.

Reason I'm looking is I have some 846 quad NAND gates with 30 ns delay (6k instead of 2k pull-ups). Have to wire them up to see if I get a predicted 8 MHz. Need to get hold of a frequency meter. Must do something with those idle ancient chips!

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Dana Myers wrote 07/17/2020 at 19:07 point

BTW, check out the logic level, ~2.7V

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