This board uses the SC26C92 to provide two serial ports and three bitbang SPI ports with some extra GPIO lines. A small amount of extra logic multiplexes and demultiplexes some the MOSI an MISO lines as well as providing 3 chip selects. This both deals with rude SPI devices that don't tristate when de-selected and ensures we have enough pins to also provide RTS/CTS on the serial lines and additional input/output lines to go with the SPI ports (eg for screens that want a C/D line or to flag service requests).

The board is as usual decoded with a 74HCT138 (U2) which allows 0x80/0x90..0xF0 ranges to be used for the 16 I/O ports the SC26C92 (U1) occupies. Pretty much nothing else is needed as the original device was aimed at the 8080/Z80 world and commonly used on S100 systems for example. The only exception is the reset signal which needs to be inverted and is inverted by the spare half of a 74HCT139 (U5).

The serial lines are fed through protection resistors to a pair of connectors on the back of the board using the same pinout as the SC126. The IP0/IP1/OP0/OP1 GPIO lines are fed the same way as they can be configured for RTS/CTS.

IP3-IP5 are general purpose input lines and routed one to each device, whilst IP6 is used for the SPI input and is demultiplexed by one half of of a 74HC153 (U3).

OP2-3 control the multiplexing of the SPI chip selects. Using a mux this way also ensures software can't select two devices at once.

OP4 and OP5 are provided as extra GPIO lines to the first two ports. OP6 provides the SPI clock and OP7 the SPI data out.

In theory it would be possible to add five further inputs using the other half of the 74HC153, IP2 and the spare SPI RX state but I've not thought of a use that makes it worth while, and there are already a lot of connectors around the board edge.

A jumper (JP1) connects the clock on the RC2014 backplane with the SC26C92. As the UART wants the standard RC2014 clock this can either be used to save fitting an oscillator, or can be used to provide the system clock as well saving a clock card. If the system backplane has no reset generator there is also a reset circuit that can be populated (but is not yet tested!).

At this point the UART side is tested and the SPI is in testing.