Projects
Discover
Contests
Courses
Stack
More
Courses
Tutorials
Events
Hackerspaces
Hackaday.com
Tindie Marketplace
Sign up
Log in
Close
FPGA + 3 R + 1 C = MW and SW SDR Receiver
Back to overview
Look mum, no ADC!
Alberto Garlassi
Back to overview
Files
3
Components
3
logs
3
Instructions
1
Discussion
0
Quantity
Component name
1
×
Lattice MachXO2 Breakout Board
3
×
10 K resistor
1
×
220 p capacitor
Alberto Garlassi