A project log for The 74's called ... (SUBLEQ)

Yetanother simple CPU of TTL chips.

michael-mllerMichael Möller 05/04/2020 at 16:300 Comments

Actually I only wanted to test the Manual Load circuit, where two monostabes trigger the Input latch and a write to the RAM. They would need to go through some sort of "OR" operation wit the signals from the MicSeq which would generate the same signals under some conditions. 

Originally I thought the MicSeq would be dead easy, as I had one (negative) logic line for each step, and a simple OR or AND would be enough for where a condition is needed. Like, "Increment PC on step 2 and 4 and on 6 if LEQ is false". But, the 74LS138 has a negative signal, and most registers trigger on an edge and need delaying until the RAM output has stabilised (ie can not trigger on the same edge). That is handled by AND-ing in the clock, so I get two edges on one step.

Note: Where it says "Seq" in the table it that step, ie Sequence5 in the ENR(EnableResult) column. I've tried to factor where I can but it still ends up with 26 gates on 7 chips (using triple-input gates doesn't help the chip count) ! And this is not even a proper instruction decoder, as there is only ONE instruction. Sigh. Defenitly will be using a EPROM in the future, but for now I wire this up. Suddenly I get worried I will rewire countless times as I discover errors, so I start using LogiSim and yes ... errors. The above is the corrected version, and below the circuit. (yeah, I could format it prettier, but that's not the point here)

If you trace backwards you can see that DOD (RAM DataOutputDisable) is simple, only one OR and NOT gate, but that the LXP (Load the indirect address register) is 5 gates.