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The NEO430 Processor

A tiny (really tiny!) msp430-native microcontroller-like processor system written in platform independent VHDL

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There is a pretty gap in the landscape of open-source soft-core processors between the tiny 8-bit processors and the chunky 32-bit ones. So I decided to fill this gap with a msp430-native 16-bit processor.

Introduction

The NEO430 is a TI msp430-native tiny microcontroller-like processor system. The system is highly configurable and provides of standard IO and peripheral components. If a certain module is not required at all it can be disabled and thus will not be synthesized. The project features Makefiles for Linux / Powershell / Windows' Linux Subsystem and provides driver libraries for all peripheral devices as well as example programs.

To get the complete information overload take a look at the NEO430 Datasheet.


Differences to the Original MSP430 Processor

The NEO430 provides full ISA-compatibility to the original msp430 CPU. However, there are some differences. Here are the most important ones:

  • Completely different processor modules with different functionality
  • Up to 48kB instruction memory and 12kB data memory
  • NEO430 tool chain (makefiles, boot-code and linker script) required for application compilation
  • No support of CPU's DADD operation
  • Different numbers of instruction execution cycles

Processor Feature

  • 16-bit open source soft-core microcontroller-like processor system
  • Full support of the original MSP430 instruction set architecture (except for the DADD instruction)
  • Code-efficient CISC-like instruction capabilities
  • Tool chain based on free TI msp430-gcc compiler
  • Application compilation scripts (makefiles) for Windows Powershell / Windows Subsystem for Linux / native Linux
  • Completely described in behavioral, platform-independent VHDL (no macros, primitives, attributes, etc. used)
  • Fully synchronous design, no latches, no gated clocks
  • Very low resource requirements and high operating frequency
  • Internal DMEM (RAM, for data) and IMEM (RAM or ROM, for code), configurable sizes
  • Customizable processor hardware configuration:
    • Optional multiplier/divider unit (MULDIV)
    • Optional high-precision timer (TIMER)
    • Optional universal asynchronous receiver and transmitter (UART)
    • Optional serial peripheral interface (SPI), 8 or 16 bit tansfer data size, 6 dedicated CS lines
    • Optional I2C-compatible two wire serial interface (TWI) supporting clock stretching
    • Optional general purpose parallel IO port (GPIO), 16 inputs & 16 outputs, with pin-change interrupt and PWM option
    • Optional 32-bit Wishbone bus interface adapter (WB32) - including bridges to Avalon (TM) bus and AXI4-Lite (TM)
    • Optional watchdog timer (WDT)
    • Optional cyclic redundancy check unit (CRC16/32)
    • Optional custom functions unit (CFU) for user-defined processor extensions
    • Optional 4 channel PWM controller with 4 or 8 bit resolution (PWM)
    • Optional Galois Ring Oscillator (GARO) based true random number generator (TRNG) with de-biasing and internal post-processing
    • Optional external interrupts controller with 8 independent channels (EXIRQ), can also be used for software-triggered interrupts (traps, breakpoints, etc.)
    • Optional NCO-based programmable frequency generator with 3 independent channels (FREQ_GEN)
    • Optional internal bootloader (2kB ROM) with serial user console and automatic boot from external SPI flash (like the FPGA configuration storage)

FPGA Implementation Results

The clock frequency has been constrained for the Xilinx and the Lattice implementation.

Xilinx Artix-7
Intel Cyclone IVLattice iCE40 UltraPlus
Full setup:
1036 LUTs, 1144 FFs, 2.5 BRAMS, 100MHz
1869 LUTs, 1137 FFs, 65800 MEMbits,121 MHz
3928 LUTs, 1923 FFs, 9 EBRs, 2 SPRAMs, 20.25 Mhz
Minimal setup (CPU + GPIO):
573 LUTs, 266 FFs, 1 BRAM
590 LUTs, 230 FFs, 49408MEMbits, 122 MHz
1812 LUTs, 755 FFs, 4 EBRS, 2 SPRAMs, 20.25 Mhz

NEO430.pdf

The neo430 data sheet

Adobe Portable Document Format - 1.14 MB - 05/19/2020 at 17:56

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  • 1 × FPGA board of choice (tested on Intel, Lattice, Xilinx)

  • 1
    Get the newest version of the NEO430 project

    Clone the NEO430 repository using git from the command line:

    git clone https://github.com/stnolting/neo430.git
  • 2
    Download the free TI msp430-gcc toolchain

    Download directly for free from TI: TI msp430-gcc compiler

    Or download a copy from github

  • 3
    Create a new FPGA project

    Open your FPGA synthesis tool (or just a simulator) of choice and create a new project. Add all VHDL files from the NEO430 rtl/core folder to your project. Make sure to add them to a new library called "neo430". neo430_top.vhd is the top entity of the processor itself - with all the interfaces coming out of it. For a simple start it might be better to use the neo430_test.vhd file as top entity (from the rtl/top_templates folder). This test setup only requires/provides a clock, a reset button, a UART interface and some fancy LEDs.

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Discussions

Yann Guidon / YGDES wrote 04/28/2020 at 20:29 point

I'm impressed ! great work !

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Stephan wrote 04/29/2020 at 12:08 point

Thank you very much!

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lvd2 wrote 04/28/2020 at 17:55 point

How does it differ from OpenMSP430 project? (https://github.com/olgirard/openmsp430)

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Stephan wrote 04/29/2020 at 14:10 point

The openMSP430 is more like a true MSP430 clone. It provides cycle accurate execution, implements BCD additions, has a full blown clock system and implements peripherals, that are 100% compatible to the original MSP430 processors. From a software point of view, the openMSP430 is treated like an off-the-shelve MSP430 by the toolchain.

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lvd2 wrote 04/29/2020 at 22:24 point

Well, so your one is something like a lightweight one with binary compatibility only, no same peripherals and no same clocks per instructions?

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Stephan wrote 05/07/2020 at 18:45 point

I see it as a different processor. It features completely different peripherals., that are more suitable (at least for me) for FPGA implementation.

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