This is the prognosed roadmap for a next generation revamp. Jupyosys development has not completely stalled, but a number of issues will not fix with the current MyHDL policy, and more features not be added. The reasons for this are hinted further below.
- Explore a different 'myhdl2' kernel concept:
- Modules are translated into MyIRL (a different representation, see below)
- MyIRL compiles into code objects
- No more conversion is taking place on the fly via AST visitors
- Revisit ShadowSignals
- Retain compatibility to MyHDL as far as:
- Good code will work
- Dirty code should spit out warnings
- Compiler options: PyPy and Cython
- Strong typing: Introduce `@component` API which will make use of type checking using the Python function argument annotation:
@component def unit(a : BulkSignal.Input, b : Signal.Output, *, FAST = True : bool) -> int: ....
Evaluate hdlConvertorAST for 'native' VHDL and Verilog output -- meanwhile, we can still use yosys RTLIL for output to V*.
- Easier to extend:
- Functions/Blackboxes: procedural instancing of (customized) primitives
- Bulk signal classes (VHDL records)
- HLS options with special signals keeping delay pipelines into account
MyIRL - a reformed syntax approach for MyHDL
The general problem with `if..else` constructs: they are conditional at run time (how obvious...). For translation into hardware this is unpractical. Ways out:
- Collect all conditions, create coverage vector table, and run the code with all possible scenarios. Painful and slow.
- Translate conditional constructs to a different representation. The following is valid Python code:
def test_if_else(a, b, q): c = AutoSig("work_c") If((a < 2) & ~(a == 0)).Then( q.set(4), c.set(1) ).Elif(a >= 3).Then( If(b > 1).Then( VarAssign(v = 1, u = a ^ b), q.set(5), c.set(3) ).Elif(b > 0).Then( q.set(9), ).Else( q.set(2), c.set(4) ) ).Else( q.set(0), c.set(0) )
The class construct behind resolves such that a structure is created internally that can elaborate into other language elements or multiplexer hardware.
Reminds you of migen/FHDL? Yes, it sure does!
The difference is, that we still author in MyHDL syntax and this intermediate representation will seldom be visible.
So we would still get the benefits of both sides:
- AST analysis before compilation
- Compileable IRL for code generation (closed source modules for evaluation by customer)