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Next generation 'myhdl2' experiments

A project log for jupyosys

..from Python Jupyter notebook to silicon

MartinMartin 04/05/2021 at 09:100 Comments

This is the prognosed roadmap for a next generation revamp. Jupyosys development has not completely stalled, but a number of issues will not fix with the current MyHDL policy, and more features not be added. The reasons for this are hinted further below.

MyIRL - a reformed syntax approach for MyHDL

The general problem with `if..else` constructs: they are conditional at run time (how obvious...). For translation into hardware this is unpractical. Ways out:

def test_if_else(a, b, q):
    c = AutoSig("work_c")
    If((a < 2) & ~(a == 0)).Then(
        q.set(4),
        c.set(1)
    ).Elif(a >= 3).Then(
        If(b > 1).Then(
            VarAssign(v = 1, u = a ^ b),
            q.set(5),
            c.set(3)
        ).Elif(b > 0).Then(
            q.set(9),
        ).Else(
            q.set(2),
            c.set(4)
        )
    ).Else(
        q.set(0),
        c.set(0)
    )

The class construct behind resolves such that a structure is created internally that can elaborate into other language elements or multiplexer hardware.

Reminds you of migen/FHDL? Yes, it sure does!

The difference is, that we still author in MyHDL syntax and this intermediate representation will seldom be visible.

So we would still get the benefits of both sides:

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