I am building a laptop with a W65C02, lots of memory, SID-sound, decent graphics and a filesystem.
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plain - 32.79 kB - 06/03/2021 at 12:44
I've worked on the extended HW version with Teensy, W65C02, memory and bank registers. Updated the schematic and did a 2-layer PCB layout. The auto-router didn't want to play so it was all done by hand. Lots of changes to pinning on the Teensy, bank-registers and memory to ease the routing. It was not possible to route by hand otherwise.
Now I'll wait a few days and then do a proper audit before I commit to an order from some Chinese PCB-manufacturer.
The new pinning means more CPU-cycles spent on the Teensy, but that is not a big problem. The major delays are because of the 74HC bank registers which are sooo slow! A CPLD would have been MUCH faster, AND easier to implement. Unfortunately my old programmer does not want to play...
Experimenting on a bread-board is very quick and works well. It is not very stable though, cables come loose too easily. I decided to build a stable HW-platform for my SW-development so I brought out the soldering iron.
The result is compact and stable, but I really don't like to mess with all the wire-cutting and soldering. Next version of the build, with external SRAM and bank registers, will be built on a professionally manufactured PCB.
Missing from this build is the connector to the screen, which will be a (small) build for another day.
No, not really. But I have worked more on the documentation and converted it to a plain text document, 78 characters wide in true retro fashion. Will print very nicely :D
When I rebuild the PZ1 HW, the SW has to wait for later. This was not ideal, so yesterday I built a second PZ1 that has only a Teensy and a 65C02 connected on a bread board. This platform is perfect for testing new 65C02 code, and also to test new HW ideas in a simulated environment.
Today I wrote a lot of code to test and document the instruction timings of the 65C02. Available documents disagree on many of the timings, and/or are very hard to decipher.
Now, if I could only find how to enclose the document...
EDIT: the pdf is now available under project files
EDIT2: updated the pdf
I've moved and that takes much more time than expected. Today was the first day in a very long time that I had an opportunity to play with PZ1. It took 2-3h to get back to the previous point since I had reinstalled the OS and build environment and the display library just had to have an older version installed. The latest version disrupts the sound for some reason :(
Since the move I have a slightly bigger hacking cave, even though the apartment is smaller. YAY!
I had some time to think about the future of my HW endeavours, and I've decided that until I get a proper CPLD (ATF1504) running, I won't change the current Teensy4.1 / 65C02 / 512KiB SRAM configuration.
An annoyance I have is that I cannot find proper/non-cryptic 65C02-docs with consistent cycle-timings. There are some holes and I really want to know! The good thing about my current HW setup is that it is possible to actually write test-code, single step it and count the cycles on a real 65C02. Code and docs coming up :D
I bought a Raspberry Pi Pico, couldn't help myself! The RP2040 is a very nice micro-controller, and the $4 is extremely cheap for what you get!
I've spent some time reading the very good datasheet to get a fuller understanding of what it can do, and I am sure that I will spend more time in the near future to try out PZ1 6502 emulation on the Pico. Such a cheap chip might be a very good fit for a nice portable 6502-computer :D
Of course I spent a lot of time coding the PIO, which is a very simple but good accelerator for doing various I/O stuff. It might be nice to create a proper VGA output from the PZ1, maybe as an add-on card...
This is the latest incarnation of PZ1:
So more real HW instead of emulation. The sound is still generated via SID-emulation on the Teensy, serial access is also done via the Teensy.
The glue logic to get memory accesses and bank registers working was nice to do in SW, so much faster and easier than doing in a CPLD. I still haven't got the CPLD programming working, will have to give up on that specific chip/programmer. The itch to get it working is still present, so I might get some ATF1504 and program them to do both glue logic and bank register functions.
Bank registers using the 74HC670 was a bit of a disappointment. They work as intended, but I had not read the data sheets thoroughly enough and the read/write-access times @3.3V are way longer than I'd thought. My memory accesses need double the time with bank registers. BUT: it works great at the speeds I use. Running the CPU @2MHz equivalent taxes the Teensy at just below 50%. No problem doing sound-generation and other I/O-tasks.
Oh how I wish the Teensy had more pins aligned for 8-bit access. Also, it is not the easiest trying to get nanosecond-level timing. An oscilloscope or using the built-in CPU-cycle counter (ARM_DWT_CYCCNT) is essential.
I still need to decide in what direction I want to pursue the HW of this project.
Next up is (re)connecting the GD3x display, and writing some 6502 multitasking demo code.
HW memory and bank registers are connected now, waiting to get them enabled and working in SW.
I did a small detour and updated the picture on memory banks and blocks. I wasn't happy with how it looked, and there were some thread variants missing. Hope this is easier to understand.
The parts I ordered from Mouser finally came, the holidays were not kind to the delivery date :)
The first revision is up and running correctly now. A Teensy 4.1 is hooked directly to a W65C02 with address, data and 6 control lines. The Teensy sets the pace by controlling the clock, so it is possible to run really slow or quite fast. I've tested the code I have to run 2 million cycles which takes around 0.285 seconds. No problem doing an emulated environment on the Teensy and still run the 6502-cpu in a 2 MHz equivalent. Not bad for such a rats nest of wires.
Everything is emulated for the 6502: memory and whatever I/O deemed necessary. This is rather nifty, since the C++ code is much easier to write than any HDL, and the emulation can even be cycle exact if needed.
This week I ordered HW: 65C02, ATF750 CPLD, 4x4 register chips and 512KiB SRAM. The urge to build a "real" HW PZ1 was simply to great.
I've done quite a lot of 3D-modeling for a compact case, but am nowhere near complete. I know what I want in the end, getting there takes time.
The code has seen little improvements since last report. Sprites are working and fun to use.
All in all, I realize I do lots of things in parallel without completing anything major. BUT it is very enjoyable, which is what matters most to me. Getting it all done is a long term goal.
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