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Theory of operation

A project log for Melba I

Melba I is an implementation of the Apple I from parts in my collection.

Christian BjelleChristian Bjelle 07/30/2020 at 18:270 Comments

A block diagram of the Melba computer is shown below, and looks pretty similar to the first page of the schematic. 

The 6502 CPU executes instructions from the RAM with some minor help in decoding the address from the CPLD. The PIA is used to read the keyboard and write characters to the Video Terminal inside the CPLD.

At first boot, however, the RAM contains random garbage, and no executable code. To make the CPU do useful work; we have to fill the RAM with a Woz-monitor and the Apple Integer BASIC in the correct locations. These has been stored inside a small SPI EEPROM, 25LC640A, and a module in the CPLD sends a read command to the EEPROM and reads the full 8192 bytes, while outputting the RAM address on the address bus and the data on the data bus. 

Filling the RAM will have to be done while the CPU is still in reset and the CPU will also have to tri-state its buses. On the Z80, the buses are tri-stated during reset, but the 6502 needs a separate pin for this.

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