Close

Control Loop Improvements

A project log for GPSDO Master Clock

A master clock source for the radio astronomy SDR DAS.

Robert RouquetteRobert Rouquette 06/17/2020 at 02:460 Comments

I noticed over the past several days, that there were occasionally momentary oscillations in the PLL feedback values.  The cause turned out to be an overlooked pole in the loop transfer function: the relative PPS offset error itself.  The PPS offset error is ultimately an integral with respect to the crystal frequency adjustment.  I solved the instability by changing my control from a simple integral into a full PID controller.  To improve the initial lock time I used two sets of coefficients:

The derivative coefficients ended up unused because the P and I coefficients provided sufficient performance by themselves.

In addition to changing the loop controller I also overclocked the xmega to 50MHz (2x 25MHz) to increase the error resolution and ultimately reduce the loop tracking error.

I also reduced the magnitude of thermal perturbations by covering the VCXO in hot glue and cooling the bottom of the board with a low speed fan.  This reduces the overall operating temperature will preventing sudden jumps in frequency from stray air currents.  The final board will have a VCTCXO and be kept in an enclosure which will further reduce thermal sensitivity.

Discussions