4k eDP LCD adaptor for MCUs

Adaptor board for sending 4k frames to a eDP LCD from an MCU. In support of my ongoing UV digital negative project

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To create an adaptor board capable of sending 4k2k (3840x2160) image frames to an eDP LCD screen. In my case for making a UV digital negative, but also for anyone wanting to build a high resolution Stereolithography (SLA) 3D printer

This is revision 3 of my work to create a high resolution UV printer for making photographic exposures with UV light. monochrome 4k LCD panels are now available with high pixel resolution aimed at the SLA 3D printer market.

  • More Options

    David Brown06/14/2020 at 15:10 0 comments

    I've been struggling to get confirmation that the 4k FIFO can actually run at high enough bandwidth. The specs indicate 9.6Bbps, but a width of 32b and 150MHz give you 4.8Gbps, with the timing diagrams showing single bit per cycle transfer and not double data rate. Would be scope to use a pair to guarantee the data rate. 

    Other options are DisplayLink DL-6000 Series. Which is a USB to HDMI / DP / eDP converter. Looks like you need to sign a NDA to get the documentation and only available through official channels. Indication is that it incorporates a frame buffer so would only need to sort HighSpeed usb 2.0 connection to send the frame data. But still waiting to hear back from the supplier rep.

    It seems that bare metal control of the Raspberry Pi is a thing. This would allow use of the MPU/GPU as just hardware without dependancy on an OS with its associated headaches. It would certainly be the lowest cost option, but brings the project down to soley a programming problem, which is so much less satisfying than hardware design.

  • Looking at best options

    David Brown06/14/2020 at 14:50 0 comments

    At the current stage of the project I have identified some key components to allow low data rate MCU to send a static image stream to an eDP LCD screen.

    1. MCU - I have an ATSAME70 dev board, but could be any MCU
    2. FPGA - I have a MAX10 - DE10-Lite dev board, but could be any FPGA that has sufficient I/O and LVDS transmitters capable of the required data rate. The MAX 10 product line is just about capable of driving 24fps 4k (4.9Gbps).
    3. 4k UHD FIFO [AL462B - Averlogic Technologies] - a dedicated 32bit FIFO for buffer and frame rate conversion, with capability of two switchable frames to allow one to be updated slowly whilst the other loops out the required data stream
    4. DSI to eDP converter [SN65DSI86-Q1 - TI] - unable to find a pixel to eDP converter for 4k, this part is MIPI / DSI to eDP. DSI has a simpler data format than eDP and also agregates 8 lanes into the 4 lanes eDP. This reduces the required bandwidth from the FPGA and means that the project should be achievable with lower cost hardware / FPGA.

    Functional diagram;

    Software modules needed;

    • SDRAM setup (use hardware SDRAMC) 16bit 256MB (C++)
    • SD access - FatFS (?)
    • graphics read - BMP, PNG (maybe) (C++)
    • Exposure frames generator (C++)
    • FPGA - I2Ccontrol system (C++)
    • DSI frame formatting / data stream to FPGA (C++)
    • SN65D - control system (C++)
    • Interface (Main, C++)
    • FPGA (VHDL) for;
      • Input buffer - 16bit to 32bit
      • FIFO write clock (sync to input)
      • Write FIFO
      • FIFO read clock (to meet DSI data rate for eDP, 150MHz)
      • Read FIFO (32bit)
      • Transmit clock (~300MHz)
      • Transmit double buffer - 8bit wide, 4bit deep
      • DSI transmitters (DDR, use FIFO read clock)
      • I2C reciever
      • Control system

    4K2K frame is ~25MB, so SAME70 SDRAM capacity for x2 frames.

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