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• Started PCB design

  roelh • 06/11/2020 at 20:46 • 1 comment

  PCB design was started.

  The dimensions will be just below 10 x 10 cm. DIN 41612 connector at one side. All SMD devices.

  4 layer pcb.

  The upper part of the pcb is now routed for the most part. In the lower part you see the ratsnest of connections that are waiting to get routed.

• First design

  roelh • 06/08/2020 at 12:57 • 0 comments

  Let's make a start with describing the design. Before I forget how everything is supposed to work. It's rather complicated.

  The schematic (at it's current state) can be found in the file section of this project. Note that most IC's are HC in the diagram but many will be AC speed types in the end. 

  When the Kobold K2 computer project started, it was intended that the cpu and video would share RAM, and that the CPU would only run during blanking time (to avoid nasty visual effects when the processor accesses RAM).

  On second thought, and also following advice in the comments, the design is now such that the processor can (almost) always run at full speed, at the cost of some extra RAM and extra buffers.

  [ place block diagrams and comments TODO ]

  CONNECTOR

  Connection to the Kobold K2 host computer is found at the top left side in the diagram. It's a 96 pin DIN 41612 connector. It's main signals are:

  • 16 bit address bus
  • 16 bit data bus
  • 5 Volt power and ground
  • RAM2_CE/ selects this card
  • MEM_WE/ writes a word to this card, if selected
  • RGB signals and two sync signals output to connector on main board
  • Several clock signals: 25, 12.5 and 6.25 MHz provided by main board
  • Indication of processor Exec/ cycle

  FRAME MEMORY

  To the processor, the card looks like a 32K-word  block of RAM, that can only be written. It will of course only write to this video frame memory when the processor does an EXEC cycle. It writes the data through the Data buffer (U6, U7) and the address is provided through the Address buffer (U8, U9). The frame memory is written when both MEM_WE/ and RAM2_CE/ are active. When EXEC is not active, it is a FETCH cycle where the processor fetches its next instruction. During this FETCH cycle, the address buffer and data buffer will be disabled, and the address will be provided by the frame counter (U10, U11). Output of the frame memory will be enabled and a "frame word" will become available every time when the processor fetches an instruction. 

  In the frame memory, only 1/4 of the available space (the upper part) is used for the frame buffer. The other 3/4 is available as general CPU RAM area. But is is not possible to execute code from this area.

  The frame counter counts at a 6.25 MHz rate, that is a new frame word every 320 nS. The counter has 16 bits, so the maximum length of a frame is 65536 x 0.32 uS = 20.9 mS. 
  

  B/W TEXT MODE

  The black&white text output has pixels of 40nS duration. The lower 8 bits of the frame are the 8 horizontal pixels of a character. The upper 8 bits tell this is a B&W  frame word.

  There are special frame words for:

  • 8 pixels data. Data will be put in shift register U15 and shifted out at 25 MHz rate.
  • horizontal sync on/off
  • vertical sync on/off
  • frame counter reset on
  • NOP

  Note that the very first instruction at address 0 in the frame memory must be an instruction to switch the frame reset signal OFF again.

  Also note that the line and frame frequency, and the polarity of the sync signals are defined by software, that has to place the special frame words at the correct position in the frame memory.

  There are several control flags (in U14) that can be switched ON or OFF by special frame words. The sync signals and the reset signal are some of them.

  SOUND SYSTEM

  A special value in the upper byte of the frame word sends the lower 8 bits to the sound register, U32. That register has a D-A converter (built from resistors) at its output. By placing such a frame word at the end of every VGA-line, or every other VGA-line, it should be possible to generate sound.

  MAIN GRAPHIC SYSTEM

  The main graphic system is also called BG (Background), because on the FG (Foreground) there can be sprites.

  Background and foreground have their own memory (both are 256K x 16). The 16 bits in BG main memory are coded as:

  URRR RRGG GGGB BBBB    

  • U is unused
  • RRRRR is a 5-bit Red value
  • GGGGG is a 5-bit Green value
  • BBBBB is a 5-bit Blue value

  Let's...

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