A new generation of TDR. The first one was fully analog, the second one was already digital and worked alone without computer, but offered limited performance (about 2.5 GHz of input bandwidth, 100 kHz sample rate and high noise floor) and limited usability without computer (only automatic mode with basic calibration).
This new generation should offer much better performance and standalone usability.
it's been 3 weeks since my last post instead of a day as was planned. Sadly, I have nothing visually interesting to show. Right now, I am working on planning of the TDR-G3 along with somewhat more complicated user interface.
The user interface will have 7" 800x480 touch LCD. It will also have the usual set of knobs and buttons found on any oscilloscope / TDR / VNA or similar devices.
The UI board will include a STM32F429ZI microcontroller which supports external SDRAM and has peripheral for driving this kind of display, 16 MB SDRAM, 16 MB NOR FLASH and several conectors for connecting the knobs / buttons / measuring boards and power supply.
I have already tested a LVGL library which looks quite promising for GUI. It has fairly reasonable memory footprint, it's fast, looks good, can be reskinned fast (even on the fly) and responds well on touch. I tested it on a STM32F469 discovery kit because I don't have the F429 kit. I managed to update the example to v7.x LVGL and enable the DMA2D. It seems this will be the way to go. It works quite fast even on the 800x480 display.
A new generation of TDR. The first one was fully analog, the second one was already digital and worked alone without computer, but offered limited performance (about 2.5 GHz of input bandwidth [for SNR=1], 100 kHz sample rate and high noise floor) and limited usability without computer (only automatic mode with basic calibration).
This new generation should offer much better performance and standalone usability. The design goals can be summarised this way:
Risetime of pulse generator should be reduced (from 85 ps to about 26 ps).
Input -3 dB bandwidth should be shifted (from <1 GHz to 8 GHz, possibly).
The noise floor should be pushed down (from -50 dB to [hopefully] at least -80 dB, possibly falling under the resolution of the instrument).
Resolution should be upgraded (from 12 bits to 16 bits).
Possibility to set the amplitude of the pulse generator to allow measurements of non-linear devices.
The user controls should be expanded from single button to full-fledged GUI with large color screen (possibly 6.5"), possibly even touchscreen (but not omitting physical controls).
I have already though out how to achieve these goals:
Use MAX3798 laser driver instead of the "slow" SY54020. The laser driver boasts ability to achieve 26 ps risetime (this will be probably limited by my board's design). It's funny that the MAX3798 is cheaper than the SY54020.
For sampling, an ADCMP582 will be used. It promises 8 GHz input -3 dB bandwidth, setup and hold times 55 ps when summed and jitter of about 10 ps. When used in "statistical mode", the effect of the jitter could be reduced.
The TDR-G2 was very noisy because I had to put an attenuator between the input and sampler due to its nonlinearity and low impedance. This pushed the useful signal deep into noise level. The TDR-G3 will only have a 3 dB splitter between the pulse generator, test connector and sampler, because the sampler is optimized to the system impedance of 50 Ω.
The TDR-G2 used internal ADC of the STM32F103. Now, an external DAC will be used for driving the ADCMP582 reference level. As of now, a DAC8562 will be used, but since it has very long settle time, it may be replaced with something less fancy and a bit faster. (Even the TDA1387 has settle time of 0.2 us, thus 50x faster than the DAC8562) The good point about the DAC8562 is its internal bandgap reference.
The MAX3798 allows for amplitude setting (it has several internal DACs, which is handy) through software. Its range isn't fabulous, but still better than having no amplitude control.
The "GUI part" will be a separate PCB, probably having a STM32F429 (it has both SDRAM capability and video generator) and SDRAM.
One part of the device already has a finished prototype (not tested yet), which you can find here.
I have been investigating ways of generating the clock signals. At first I wanted to use the SY89296 ECL delay line just like Ted Yapo did. However, I stumbled upon the Si5341/40 PLLs which allow setting the mutual phase of its outputs in <1 ps steps. However, after some investigation, it turned out to be a typical marketing bogus. The part allows you to set the phase, but the tolerance of the setting is ± 100 ps which means that lower 8 or 9 bits of the setting are useless. I don't know why, but SiLabs cannot manage to have at least one document without major errors, requiring you to read patiently through each document and every version of each document to spot the "strange" things. The same applies to their devices...
So, the device will now work with the Si5341 in the same mode of operation like the Si5351 did in TDR-G2. It will output two clocks maybe 2 ppm apart. I have to stop writing now, this log will be finished later today or yesterday.