The same HD63C09E from my previous project, but 256KB of SRAM and a significant CPLD upgrade to MAX10. This allows eliminating the Zilog SCC and CIO chips that I used previously. An onboard 5V DC-DC converter and 3.3V LDO allow this SBC to be powered from 6-16V input, in addition to allowing USB power. Two VCP comfortably support NoICE debugger and console I/O. Finally, the obsolete Epson RTC chip is replaced with a DS3231M. The goal is semi-compatibility with the SBC V1.0.