Introduction

A counter is a digital circuit which is used for counting input events (pulses, edges). Digital electronic counters are usually built from a series of flip-flops connected in cascade.

This project is intended to show how to build bidirectional counters (FSM) having different interface methods designed in GreenPAK. The methods to be implemented are:

  • 16-bit FSM with SPI output
  • 16-bit FSM with I2C output
  • FSM with parallel outputs (based on glue logic)

Below we described steps needed to understand how the bidirectional counter has been programmed to design the analog clock motor driver. However, if you just want to get the result of programming, download GreenPAK software to view the already completed GreenPAK Design File. Plug the GreenPAK Development Kit to your computer and hit the program to design the counter.

  1. "16-bit FSM with SPI Output"

Figure 1: “16-bit FSM with SPI Output”

The “16-bit FSM with SPI output” counts input clocks in an internal 16-bit register (FSM0, FSM1), at any time a user can read the value via SPI, reset the 16-bit register, or change direction of counting. The design is implemented in SLG46140, or SLG46620 as well. 

Let’s see how it works. The 16-bit counter is implemented using two counters (FSM0 and FSM1 blocks) with additional logic, since SLG46140 doesn’t have 16-bit FSM. Bits 15 – 8 are stored in FSM0, Bits 7 – 0 in FSM1. Both FSMs are connected to the SPI block, which can output serial data via SPI. The direction of counting is controlled by Up/Down pin. If this pin is HIGH, the system counts UP, if this pin is LOW, the system counts DOWN. Gen Reset pin is used to reset counter value (active HIGH).

Input clocks come from Clock input. These clocks are applied simultaneously at CLK inputs of FSM1 and FSM0. FSM1 counts each clock, whereas FSM0 counts only when FSM1 counter value is 255 and Up/Down signal is HIGH or when FSM1 counter value is 0 and Up/Down signal is LOW. This functionality is achieved using KEEP input of the FSM0. When this signal is HIGH the counter value of the FSM0 is not changing despite the clock signal. The KEEP input is connected to FSM1 output through an inverter. FSM1 output in turn is HIGH only when counter value is 0 and Up/Down signal is LOW, or when counter value is 255 and Up/Down signal is HIGH.

Since FSM counter value is reset to counter data when the FSM counter value reaches maximum (255) and FSM1 counter data is 255, FSM1 stops at a max value (255) when counting up and FSM1 UP input signal is HIGH. In order to avoid this situation, DFF2 and 3-bit LUT1 reset FSM1 by the next clock when FSM1 reaches max value and Up/Down is HIGH. If Up/Down is LOW, FSM1 is not reset. The situation is similar with FSM0. This one is also reset to counter data, and when FSM0 reaches max value (16383) it will then start to cause incorrect data. In order to avoid that situation, 3-bit LUT3 resets FSM0 by the next clock when both FSMs reach max value (SPI output code in this situation is 0xFFFF) and Up/Down is HIGH. Both FSMs are not reset if Up/Down is LOW.

D0 – PIN#6 (nCSB)

D1 – PIN#7 (SCLK)

D2 – PIN#12 (MISO)

D3 – PIN#2 (Gen Reset)

D4 – PIN#3 (Up/Down)

D5 – PIN#4 (Clock)

Figure 2: Functionality of “16-bit FSM with SPI Output”

The following design, which is shown on Figure 3, is just a modification of the 16-bit FSM with SPI output. This design can be used if we need to detect an overflow (OVF) event and set the initial value of the 16-bit counter (FSM0 and FSM1).

The initial value of the 16-bit counter is set to ½ maximum value (FSM0 data = 0x7F, FSM1 data = 0xFF) and can be adjusted easily. Initial value setting process takes ~9ms and starts just after the power up of GreenPAK IC, or when High pulse is applied to “Gen Reset” input. During those ~9ms FSM0 and FSM1 receive pulses from the internal OSC and will ignore pulses from Clock input. The initial value depends on CNT0 counter data and Pipe...

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