After a few days of messing around with the FPGA top entity, I got it running and was rewarded with the TS2BUG prompt on the VDU.
FPGA implementations of CPUs rarely match the pins of the original part. They are typically poorly documented where it comes to the changes or how to interface to the CPU. Sure, address and data match and are easy. The 68000 Hardware User Manual helps for signals that are in common but doesn't help for missing/added signals.
Just like the 68000, the VHDL code has lower and upper Data Strobes (UDS* and LDS*). The relationship to the clock is not documented. For the real 68000, the Data Strobes can be used to gate writes since the data is valid before DS drops and remains valid after DS rises. That is shown below where the red box is the data strobe for reads and the green box is the data strobe for writes. Note the write strobe is shorter.
That's not the way it works with the VHDL code.
In the end there's nothing like hooking up a logic analyzer and looking at the signals to straighten things out.
Turns out gating the CPU clock (low) with the Data Strobe works for writes. Took a while to figure that one out. I wish the designers would put just a few notes on differences to the real parts when they make them but I am greatful that someone did the heavy lifting in the design.
The CPU runs fine at 25 MHz.