More SRAM than TS2

A project log for Retro 68000 CPU in an FPGA

Making a Retrocomputer with a 68000 CPU in an FPGA 08/11/2020 at 20:440 Comments

The resource utilization in the 5CEFA2F23 FPGA Card is:

There's more than enough left over block memory to have 128KB of SRAM. The only complication is that the TS2 memory map wasn't designed for more than 32KB. That is because it places the EPROM above the SRAM in the memory space.

The monitors TS2BUG and TUTOR could be re-assembled to move the ROM to higher memory.

The 5CEFA2F23 FPGA Card also has 32MB of DRAM which could be used as system memory and it's organized as 16MB x 16-bits which is ideal. The 24-bit address space of the 68000 only allows 16 MB to be addressed so not all of the DRAM could be mapped to the memory space. And it might require wait states for memory access.

Alternately, the fast SRAM in the FPGA could function as a cache memory but would require a much more complicated controller. DRAM does bursts quite nicely and it could fill a cache line pretty efficiently.

I think I will start with getting 128KB of SRAM working first.

Changes to Monitor Code

This ought to be as easy as changing the .ORG statement to point to the new ROM base address and changing the address decode in the FPGA.  The assembly code to change the ROM base address is:

         .ORG    0xF80000

Here are the instructions to make the ROM file.

Changes to memory map

The peripherals are currently located at 0x01______ addresses and should be moved up as well. I will put the ROM from 0xF80000 to 0xFFFFFF and the I/O to start at 0xF00000 which would allow up to 512KB of ROM

The new ROM chip select VHDL code is:

w_n_RomCS <= '0' when (cpuAddress(23 downto 19) = x"F"&'1')        else         -- xF80000-xFFFFFF(MAIN EPROM)
             '0' when (cpuAddress(23 downto 3) =  x"00000"&'0')    else        -- X000000-X000007 (VECTORS)

The new RAM chip select VHDL code is:

w_n_RamCS <= '0' when ((w_n_RomCS = '1') and (cpuAddress(23 downto 17) = x"0"&"000"))    else    -- x000008-x01ffff (128KB)

I saved new versions of both the monitor source code and FPGA and am working with the new versions.

The I/O map changes to:

PDI1     =       0xF00000       | PARALLEL PORT ADDRESS
PITPCDR  =       0xF00019       | PORT C DATA REGISTER
PITTCR   =       0xF00021       | TIMER CONTROL REGISTER
PSTATUS  =       0xB            | PRINTER STATUS
PDATA    =       1              | PRINTER DATA
SER1     =       0xF00040       | TERMINAL
SER2     =       0xF00041       | SERIAL PORT2 ADDRESS

I need to get the 68K assembler working. Jeff Tranter had a Linux build he used for his assembly. I will probably try and get it installed on a Raspberry Pi. Here's the installation instructions.