Added GPIO ports to FPGA design.

Features

• Input/Output ports
• 3 bit port
• (2) 8 bit ports
• Two locations from CPU
  • Register/port selection - indirect
    • Set bit direction
  • Data port
• Connects to J2 connector

Indirect Register

-- 0 DAT0 bits [2:0]
-- 1 DDR0 bits [2:0]
-- 2 DAT2 bits [7:0]
-- 3 DDR2 bits [7:0]
-- 4 DAT3 bits [7:0]
-- 5 DDR3 bits [7:0]

Data Direction Register Bits

-- 0 in the data direction register marks the bit as an output
-- 1 in the data direction register marks it as an input

After reset, GPIOADR=0, all DDR*=0 (output) all DAT*=0 (output low). 

Route to DB-25 on MultiComp in a Box design.