Xosera - FPGA-Based Retro Video Graphics

Xark's Open Source Embedded Retro Adapter - Retro graphics display for rosco_m68k and similar retro computers

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Xosera is an FPGA based video adapter designed with the rosco_m68k retro computer in mind. Inspired in concept by it's "namesake" the Commander X16's VERA, Xosera is an original open-source video adapter design, built with open-source tools, that is being tailored with features appropriate for a Motorola 68K era retro computer. Features VGA video generation at 640x480 or 848x480 (16:9 widescreen) resolution, flexible register based interface, dual overlaid video playfields each with 256 color colormap, tiled and bitmap modes with 16 or 256 colors (or 4096 colors blending both playfields), screen synchronized co-processor (ala "copper"), fast asynchronous blitter with logical operations, transparency and shifting.

Xosera is an FPGA based video adapter designed with the rosco_m68k retro computer in mind (and likely adaptable to most any computer with an 8-bit parallel port and a few control signals).

"Not as clumsy or random as a GPU, an embedded retro video adapter for a more civilized age."

Inspired in concept only by it's "namesake" the Commander X16 VERA, Xosera is an original open-source video adapter design, built with open-source tools, that is being tailored with features generally appropriate for a Motorola 68K era retro computer.

Currently the design is using the Lattice iCE40UP5K FPGA which is fully supported by the open Yosys FPGA tools. Development is now mostly on the Xosera board (PCB available on Tindie) for the rosco_m68k system using the UPduino 3.x FPGA board, but still also builds for the iCEBreaker FPGA board (which can alter Xosera registers via USB to SPI).

Current Xosera features include:

  • VGA output at 640x480@60Hz or 848x480@60Hz (16:9 widescreen 480p)
  • Register based interface using 16 16-bit main registers (accessed 8-bits at a time)
  • 128KB of embedded main video RAM (limited by current modest FPGA)
  • 10KB of tile RAM for tilemaps or tile glyph definitions (or either can be stored in main VRAM)
  • Xosera memory accessed via multiple 16-bit read/write ports with auto-increment and nibble write masking
  • Dual 256 x 16-bit ARGB colormap RAM (16 "blend" values and 4096 colors), one colormap palette per video "playfield"
  • Dual overlaid video "playfields" with 4-levels of "alpha blending" or additive blending (wrapping or saturating)
  • 8x8 or 8x16 tile based display modes (with adjustable displayed height, e.g., for 8x11)
  • 1-bit tiled mode allows 256 8x8/8x16 glyphs (8-bit) and 16 forground/background colors (similar to PC text mode)
  • 4-bit and 8-bit tiled modes allow 1024 8x8 glyphs (10-bit), H and/or V mirroring and 16 colormap choices (similar to some consoles)
  • 1-bit bitmap mode with 16 foreground/background color attribute byte (similar to a bitmapped PC text mode)
  • 4 or 8-bit "chunky pixel" bitmap modes with 16 or 256 colors (128KB VRAM permitting, pixel doubling required for full bitmap at 256 colors)
  • Horizontal and/or vertical pixel replication, so pixel size can be from 1x1 up to 4x4 native pixels (e.g., for 320x240 mode)
  • Fractional horizontal and/or vertical scaling (e.g., to allow scaling to modes like 640x400 or 512x384 using non-uniform pixel size)
  • Smooth horizontal and vertical tile scrolling (with native pixel resolution scrolling offset)
  • Amiga-inspired video-synchronized co-processor ("copper") to alter video display registers or colors on the fly
  • Rectangular bitmap "blitter" with support for logical operations, transparency, masking and shifting (~10 million words/sec)
  • Interrupt generation with maskable interrupt sources including end-of-frame, copper generated, bliiter idle
  • C API that provides easy low-level register access (and transforms into efficient inline 68K assembly code)
  • Robust ANSI (aka DEC VT) compatible C terminal driver for rosco_m68k (included in recent rosco_m68k firmware)
  • Implemented in a System Verilog subset, that is synthesizable and compatible with current versions of the open FPGA tools.
  • GNU Make based build using the pre-built YosysHQ OSS CAD Suite Builds tested on Linux (Ubuntu 20.04 and also Ubuntu on RPi4 and RISC-V 64), Windows 10 and MacOS.
  • Fast Verilator simulation with host bus emulation (to alter Xosera registers in simulation and upload data) and using SDL2 for PNG screenshot of each video frame
  • Icarus Verilog simulation

Planned Xosera features TODO:

  • DVI/HDMI output at 640x480@60Hz or 848x480@60Hz (16:9 widescreen 480p) using 1BitSquared DV PMOD (currently this mostly works, but is not 100% solid at this point - not exactly sure what the issue is).
  • 4 dual 8-bit (stereo) audio channels with full channel mixer for stereo audio output similar to Amiga (using sigma-delta DAC output)
  • At least one "cursor" sprite above video playfields (and ideally more, probably with 16...
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  • Xosera prototype PCB up and running!

    Xark04/18/2021 at 04:51 0 comments

    After a bit of a lull, Xosera development has heated up recently after @Ross Bamford designed a bus interface for his #rosco_m68k retro computer.  This inspired me to get it actually up and running on a real computer (vs the "tech-demo" it has been).  The prototype PCB uses an Upduino 3.0 FPGA board (available from Tindie). This board breaks out all iCE40UP5K FPGA pins and Xosera uses all of them (with one input-only pin to spare).  The rest of the PCB is mostly 3.3v/5v voltage level shifters and programmable GALs to handle the full m68k bus signals (this FPGA doesn't have enough pins for the full m68k bus).  The prototype uses a dual PMOD header to connect either a Digilent VGA PMOD or 1BitSquared DV PMOD both of which provide a 4096 color image in 640x480 or 848x480 (16:9 480p) with Xosera.

    The Xosera "bus interface" consists of a bi-directional 8-bit parallel data bus, along with a 4-bit register address, byte select signal (like a low address bit) along with read-not-write and a chip-select.

    For the rosco_m68k computer this is mapped into the address space "8-bit 6800 style" where only half of the 16-bit 68k data bus is hooked up.  The 68k has a special instruction to write data to "odd bytes" only called MOVEP, that allows you to do a reasonably fast 16 or 32-bit access to an 8-bit peripheral (like Xosera).

    There were a few issues getting the bus interface working with the rosco_m68k, but we mostly ironed those out with everything splayed out on a breadboard.  The main problems were some issues with sampling the data bus one cycle too early and some minor issues getting the FPGA tri-state working properly so the CPU can do reads from Xosera.  We also added a simple "glitch filter".  The FPGA samples the 68k bus at the pixel clock frequency (typically about 25 or 33 MHz) and seems to have no trouble keeping up with the 8/10 MHz 68k without any DTACK or wait states (the 68k bus uses several cycles for a memory transaction).  Here is an "exciting" picture of the first time 68k was able to draw anything (well, we were pretty excited 😅).

    Since we had been testing with a breadboard setup we were hopeful, and Ross informed me the PCB worked on his first test (I am still awaiting my PCB to cross the ocean).  Ross has coded up the start of a little "Snake" game on the rosco_m68k in 68000 assembler.

    Now the main thing is to add more cool features to the "gateware" (the programmable "hardware" design in the FPGA).  Currently it is text mode with 8x8 or 8x16 16 color text mode (with re-definable font, with 8KB tile memory), 256 color palette, and basic ability to set VRAM display address, fine scroll, text size etc.

    I'd like to have 2 planes of 16-color graphics (probably pixel-doubled, or using tile mode, since just 128KB of VRAM) and one page of 256-color.  Something that is in the same ballpark with classic Atari ST or Amiga graphics (but not a clone of any system).

    There is a basic blitter, but it is not fully wired up yet (it is used to clear VRAM at init).  Here is a link to the current WIP "register map" (subject to change).

    I have a breadboard setup using an 8MHz 3.3v AVR pro mini that has also been fun to do some testing with while I wait for my PCB.  Xosera is probably pretty easy to get working with most any parallel bus or I/O port (like 8-bit computers etc.).  Here is my AVR setup using a DV PMOD at the end of a ribbon-cable "braid".
    Here is an animated GIF showing the output of a quick and dirty testing program for Xosera executing on the AVR.  The AVR can write to all 128KB of VRAM in about 66 milliseconds (or painfully slower if you use the Arduino GPIO library calls).

    Still early in development (in earnest), but seems a promising start.  Now I am working on some graphics features as well as adding the ability to read/write to the "bus registers" via SPI or UART (to make testing easier from PC, and...
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zpekic wrote 12/09/2021 at 00:26 point

Cool project! I kinda have the reverse - from old VDP to FPGA. I wonder if your board could be extended to capture signals from VDP and convert to VGA. Or maybe it could do that in a window?

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Xark wrote 12/15/2021 at 22:58 point

Yes, your project is quite interesting too.  I do think, given a few spare pins, Xosera could perhaps capture the RGB VDP output and maybe scan-double and composite it instead of an overlay playfield B or similar.

I have a few "follow on" Xosera ideas and experiments, such as this one once the base Xosera design is complete (currently working to finish up "blitter" and then hopefully squeeze in some audio).


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zpekic wrote 12/16/2021 at 05:18 point

Awesome! Good luck with the tinkering, can't wait to see where it takes you!

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jbaum81 wrote 07/13/2021 at 06:04 point

Hi pretty cool project, I may try to implement your progress on my 65c02 project. Not sure if your married to the PTH IC's for your expansion card, but I'm using a SN74HCT245ANSR to interface my 6502's 5v bus to the upduino 3.0, works a treat. Also see your using a couple spld/gals and a flipflop, I've been playing with the Atmel ATF1504's with some success.

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