Xosera - FPGA-Based Retro Video Graphics

Xark's Open Source Embedded Retro Adapter - Retro graphics display for rosco_m68k and similar retro computers

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Xosera is an FPGA based video adapter designed with the rosco_m68k retro computer in mind. Inspired in concept by it's "namesake" the Commander X16's VERA, Xosera is an original open-source video adapter design, built with open-source tools, that is being tailored with features appropriate for a Motorola 68K era retro computer. Features VGA or DVI video generation at 640x480 or 848x480 (16:9 widescreen), register based interface (with auto-increment and "blitter" planned) along with an SPI interface for easy development and testing.

Xosera is an FPGA based video adapter designed with the rosco_m68k retro computer in mind (and adaptable to similar systems).

Currently the design is supported for the iCE40UP5K FPGA which is fully supported by the open Yosys/NextPNR tools. Development is being done on the iCEBreaker FPGA board with the rosco_m68k prototype PCB using an embedded Upduino 3.0 board (uses every GPIO pin).

Planned Xosera features:

  • Second overlaid video play-field (with transparent color)
  • Sprite for mouse cursor (and possibly other sprites)
  • 4 stereo 8-bit audio channels with full mixing with sigma-delta DAC
  • "Blitter" to accelerate copy and fill operations as well as 2D drawing
  • Line-draw and polygon acceleration

Current Xosera features:

  • VGA or HDMI (DVI) output at 640x480@60Hz or 848x480@60Hz (16:9 widescreen 480p)
  • 128KB of embedded video RAM (embedded SPRAM in iCE40UP5K)
  • 256 color palette out of 4096 colors (12-bit RGB)
  • Screen synchronized "copper" processor for on-the-fly video changes without interrupts
  • V-blank, scan-line, draw done and other interrupt support
  • 1-BPP (with color attribute), 4-BPP (16-color) and 8-BPP (256 color) support
  • Bitmap and tiled modes for all BPP.  Tiles can be in VRAM or dedicated 8KB tile RAM
  • Smooth horizontal and vertical pixel scrolling
  • Up to 8x16 tile size with 4-bit foreground/background color per character in text mode
  • Full featured ANSI compatible terminal driver for rosco_m68k system.
  • Multi-colored tiled modes for graphics supporting up to 1024 tiles and H, V mirroring
  • Made with fully open tools using GNU Make and the excellent pre-built open FPGA tool binaries from OSS CAD Suite (builds on Linux, Windows 10 and MacOS etc.).
  • Fast Verilator simulation using SDL2 for PNG screenshot of each video frame
  • Icarus Verilog simulation
  • SPI interface to registers for development from PC via FTDI (handy with iCEBreaker FPGA)

  • Xosera prototype PCB up and running!

    Xark04/18/2021 at 04:51 0 comments

    After a bit of a lull, Xosera development has heated up recently after @Ross Bamford designed a bus interface for his #rosco_m68k retro computer.  This inspired me to get it actually up and running on a real computer (vs the "tech-demo" it has been).  The prototype PCB uses an Upduino 3.0 FPGA board (available from Tindie). This board breaks out all iCE40UP5K FPGA pins and Xosera uses all of them (with one input-only pin to spare).  The rest of the PCB is mostly 3.3v/5v voltage level shifters and programmable GALs to handle the full m68k bus signals (this FPGA doesn't have enough pins for the full m68k bus).  The prototype uses a dual PMOD header to connect either a Digilent VGA PMOD or 1BitSquared DV PMOD both of which provide a 4096 color image in 640x480 or 848x480 (16:9 480p) with Xosera.

    The Xosera "bus interface" consists of a bi-directional 8-bit parallel data bus, along with a 4-bit register address, byte select signal (like a low address bit) along with read-not-write and a chip-select.

    For the rosco_m68k computer this is mapped into the address space "8-bit 6800 style" where only half of the 16-bit 68k data bus is hooked up.  The 68k has a special instruction to write data to "odd bytes" only called MOVEP, that allows you to do a reasonably fast 16 or 32-bit access to an 8-bit peripheral (like Xosera).

    There were a few issues getting the bus interface working with the rosco_m68k, but we mostly ironed those out with everything splayed out on a breadboard.  The main problems were some issues with sampling the data bus one cycle too early and some minor issues getting the FPGA tri-state working properly so the CPU can do reads from Xosera.  We also added a simple "glitch filter".  The FPGA samples the 68k bus at the pixel clock frequency (typically about 25 or 33 MHz) and seems to have no trouble keeping up with the 8/10 MHz 68k without any DTACK or wait states (the 68k bus uses several cycles for a memory transaction).  Here is an "exciting" picture of the first time 68k was able to draw anything (well, we were pretty excited 😅).

    Since we had been testing with a breadboard setup we were hopeful, and Ross informed me the PCB worked on his first test (I am still awaiting my PCB to cross the ocean).  Ross has coded up the start of a little "Snake" game on the rosco_m68k in 68000 assembler.

    Now the main thing is to add more cool features to the "gateware" (the programmable "hardware" design in the FPGA).  Currently it is text mode with 8x8 or 8x16 16 color text mode (with re-definable font, with 8KB tile memory), 256 color palette, and basic ability to set VRAM display address, fine scroll, text size etc.

    I'd like to have 2 planes of 16-color graphics (probably pixel-doubled, or using tile mode, since just 128KB of VRAM) and one page of 256-color.  Something that is in the same ballpark with classic Atari ST or Amiga graphics (but not a clone of any system).

    There is a basic blitter, but it is not fully wired up yet (it is used to clear VRAM at init).  Here is a link to the current WIP "register map" (subject to change).

    I have a breadboard setup using an 8MHz 3.3v AVR pro mini that has also been fun to do some testing with while I wait for my PCB.  Xosera is probably pretty easy to get working with most any parallel bus or I/O port (like 8-bit computers etc.).  Here is my AVR setup using a DV PMOD at the end of a ribbon-cable "braid".
    Here is an animated GIF showing the output of a quick and dirty testing program for Xosera executing on the AVR.  The AVR can write to all 128KB of VRAM in about 66 milliseconds (or painfully slower if you use the Arduino GPIO library calls).

    Still early in development (in earnest), but seems a promising start.  Now I am working on some graphics features as well as adding the ability to read/write to the "bus registers" via SPI or UART (to make testing easier from PC, and...
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zpekic wrote 12/09/2021 at 00:26 point

Cool project! I kinda have the reverse - from old VDP to FPGA. I wonder if your board could be extended to capture signals from VDP and convert to VGA. Or maybe it could do that in a window?

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Xark wrote 12/15/2021 at 22:58 point

Yes, your project is quite interesting too.  I do think, given a few spare pins, Xosera could perhaps capture the RGB VDP output and maybe scan-double and composite it instead of an overlay playfield B or similar.

I have a few "follow on" Xosera ideas and experiments, such as this one once the base Xosera design is complete (currently working to finish up "blitter" and then hopefully squeeze in some audio).


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zpekic wrote 12/16/2021 at 05:18 point

Awesome! Good luck with the tinkering, can't wait to see where it takes you!

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jbaum81 wrote 07/13/2021 at 06:04 point

Hi pretty cool project, I may try to implement your progress on my 65c02 project. Not sure if your married to the PTH IC's for your expansion card, but I'm using a SN74HCT245ANSR to interface my 6502's 5v bus to the upduino 3.0, works a treat. Also see your using a couple spld/gals and a flipflop, I've been playing with the Atmel ATF1504's with some success.

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