SIFP - Single Instruction Format Processor

Just as advertised - processor with 1 instruction format, 1 word per instruction, and grand total of 16 states.

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This is a placeholder for now, but I plan to:

write the CPU in VHDL
"wrap it" in a simple system with RAM/ROM/VGA/UART for debug/demo/development purposes
extend/change my microcode complier to become the assembler for the CPU (yet, 1 abstraction level down!)
document as much as I can

CPU will:

execute each instruction in 2 cycles (fetch + execute)
each execute cycle can do up to 5 operations in parallel
out of those 5 operations, there can be max 1 memory read or write
almost every cycle is a memory cycle, CPU utilizes the memory over 95% of time
be microcoded, with exactly 16 microinstructions, each of which is also a separate CPU state
always execute only those 16 microinstructions - with one small exception...
be 16-bits wide for illustration purposes but can be of any width

Here is the instruction format:


Where P, A, X, Y, S are bits controlling the internal PC, A, X, Y and S registers. There is also a "hidden" F (s

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