This project is in progress and lot of it is already working:

-write the CPU in VHDL
-"wrap it" in a simple system with RAM/ROM/VGA/UART for debug/demo/development purposes (virtual "Single Board Computer"
- extend/change my microcode complier to become the assembler for the CPU
- write boot / monitor program using the assembler, and run it on the SBC
-document as much as I can

CPU is:

-executing each instruction in 2 clock cycles (fetch + execute)
-able to execute up to 5 operations in parallel in each clock cycle
-out of those 5 operations, there can be max 1 memory read or write
-memory efficient, almost every cycle is a memory cycle, CPU utilizes the memory over 95% of time
-supports 16 bit data width and 16 bit address bus
-able to work in Harvard and Von Neumann modes

Stay tuned for updates here, or look directly in github