Inspired by an architecture from my professor, which we implemented back in my VHDL lecture, I redesigned it, cut it a bit down and gave it a go in verilog. Also a bit xilinx picoblaze influence
Goal it is to just build my own CPU, Compiler and maybe add some peripherals later - Let's see where this goes.
ICE stands for "IC-Entwurf" (IC design), as the module from my prof is called like that
16 Bit word width
16 bit register width
(Maybe I have to extend the word width and instructions later, especially for interrupts - lets see...)
First of I've rewritten everything in VHDL, because the very first version of my processor was in VHDL and I feel much more confident with writing it than verilog.
As a second step I implemented a very basic BRAM module, tested most instructions (i just realized while typing this that I am still missing the shift instructions. Lazy me.) with a testbench and wired up the SoC.
Created a simple ROM too which is for the moment directly in the SoC module file and contains just 32 instructions max for the moment, BUT I got the very first program working looking like this:
load 0 into r0 load 1 into r1 load 16 into r2 load 0 into r3 load 5 into r5 add r0 = r0 + r1 set address (leds) 0x5 to r0 set lower than r3 = r1 < r2 branch when r3 != 0 --> 5 (to add instruction) sub r0 = r0 - r1 set address (leds) 0x5 to r0 set lower than r3 = r0 < r1 branch when r3 = 0 --> 9 (sub instruction) jump 0
This counts to 16 and back down to 0. And this works super nice! See embedded video:
Pretty happy about this. I think I will implement a very very simple assembler first, a nice ROM module next and then will see where it goes on. The updated VHDL code can be found in my gitlab repository