The NEORV32 Processor is a customizable microcontroller-like SoC based on the NEORV32 RISC-V-compliant CPU.
It is intended as auxiliary processor within larger SoC designs or as stand-alone custom microcontroller. The processor provides common peripherals like GPIO, serial interfaces, timers and embedded memories. All features beyond the base CPU are optional and can be configured via VHDL generics.
The project comes with a complete software ecosystem that features core libraries for high-level usage of the provided functions and peripherals, application makefiles , a run-time environment, several example programs and even a freeRTOS port.
The project is intended to work "out of the box " - just synthesize the provided test setup, upload it to the FPGA board of choice and start playing with the NEORV32.
Also check out the project boards on GitHub to see what I'm currently working on and which further features are in the pipeline.
- NEORV32 CPU: RISC-V-compliant rv32i CPU (passes the official RISC-V compliance tests) with optional extensions:
- A - atomic memory access instructions
- B - bit manipulation instructions (Zbb subset)
- C - compressed instructions (16-bit)
- I - base integer instruction set
- E - embedded register file (reduced register file size)
- M - integer multiplication and division hardware
- U - less-privileged user mode
- X - NEORV32-specific CPU extensions
- Zfinx - Single-precision floating-point extension
- Zicsr - Control & status registers (allows interrupts and exceptions)
- Zifencei - Instruction stream synchronization (e.g. for self-modifying code)
- PMP - Physical memory protection
- HPM - hardware performance monitors
- Interrupt: RISC-V timer, software & external interrupts + 16 fast interrupts + 1 non-maskable interrupt
- NEORV32 Processor: Full-scale RISC-V microcontroller system / SoC with optional submodules
- optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
- timers (watch dog, RISC-V-compliant machine timer)
- serial interfaces (SPI, TWI, UARTs)
- general purpose IO and PWM
- dedicated NeoPixel(TM) LED interface
- external bus interface (Wishbone / AXI4)
- Software framework:
- core libraries for high-level usage of the provided functions and peripherals
- application compilation based on GNU makefiles
- GCC-based toolchain (pre-compiled toolchains available)
- bootloader and runtime environment
- several example programs
- doxygen-based documentation: available online on GitHub pages
- FreeRTOS port available
- Full-blown data sheet based on asciidoc
- Completely described in behavioral, platform-independent VHDL - no primitives, macros, attributes, etc.
- Fully synchronous design, no latches, no gated clocks
- Small hardware footprint and high operating frequency
- Tested on real hardware (Xilinx, Intel and Lattice FPGAs)
- Example setups for various FPGA boards to get you started
- Arty A7 (Xilinx Artix-7)
- UPduino (Lattice ice40 UltraPlus)
- DE0-nano (Intel Cyclone IV)
- From zero to "hello word": Completely open source and documented.
- Plain VHDL without technology-specific parts like attributes, macros or primitives.
- Easy to use – working out of the box.
- Clean synchronous design, no wacky combinatorial interfaces.
- Be as small as possible – but with a reasonable size-speed trade-off.
- Be as RISC-V-compliant as possible.
- The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 22+ MHz.