• More thoughts on the project

    Courtney • 08/10/2021 at 09:22 • 0 comments

    I still haven't started my Verilog CPU project. I've been wanting to build upon the Gigatron using a Digilent CMOD A7-35t FPGA board. I've gone through various ideas in my mind and have discarded many. I'd like to make something that can run vCPU code, but with a different architecture. I'm looking for pointers/comments/thoughts on various aspects or any considerations. I ask that I not be condescended to or told the obvious.

    Separating I/O from the CPU using DMA -- One of the first changes I'd like to make would be to use some variety of DMA to read the frame buffer directly and honor the indirection table. The indirection table system is nice since it eliminates the need for blitting when you want special effects (virtualization is faster than copying entire lines). Since the video is 160 bytes wide and the X register addresses 256 bytes, you can change the indirection table to side-scroll one or more lines. Racer uses that for side-scrolling. If you don't want much of a background on the sides, you can take advantage of the register wrap-around and use the same background for both sides. So I'd want my controller to be table-aware. The sound, keyboard, and likely other I/O will also be done in hardware so everything can have direct access to the syncs and thus avoid hardware race conditions. There could be ways to mitigate software race conditions such as creating a CPU halt line. Line quadding will be done in hardware, possibly using a BRAM buffer, so the SRAM is only read 1:4 native scan lines.

    Then, of course, moving only the video to hardware introduces a new problem. Everything else needs to be synced with the video controller. In the Gigatron (proper), the ROM bit-bangs the video and syncs, and the user code is aware of the syncs. Two different ideas come to mind. One is to add other controllers to the video controller. Since it will be the DMA "bus master," it could take over the software-created sound and do it the same way, and it would know when it is safe to poll the keyboard. Concurrent DMA would be used for not only the video controller, but also sound, keyboard, and possibly other I/O.

    One issue I see with moving everything to DMA (and using the video controller as the bus master and arbiter) is software races. Doing all the I/O in hardware like that would remove any chances of hardware race conditions, but it could cause software races. So I'd likely need to find a way to add halting or spinlocks. For instance, to run legacy Gigatron vCPU code, I'd likely want to add a mode that pauses the CPU while the lines are drawn. That will make the hardware similar enough to probably prevent races and allow original vCPU code to work as expected. 

    Of course, using interrupts could be another way to route the signals at the correct time and provide the needed code to service the ports when they are active. That would allow for more complex I/O than outlined above and make it easier to add other things. For instance, I could have a couple of interrupt-driven SPI ports. Interrupts are not a part of the SPI standard, nor are they forbidden. Discretion is left to the designer.

    6-bit sound -- Since Blinkenlights are not planned, I might as well implement 6-bit sound. The custom hardware would work during the DMA time and would use the same memory locations as now. I'd like to try to mux this on the color lines. Demuxing might be done using 2 multiplexer sets to decide what gets selected and what gets blanked or muted. Hopefully, interference won't be a problem. I'm unsure about the best way to do this. I'd like to try this to save GPIO pins.

    Advanced memory unit/arbiter -- This unit should be able to use 10ns SRAM, make it synchronous, give it 2-3 "ports," allow 16-bit SRAM transfers using the best available method (do during the next cycle, do during unused video cycle or sync time, or halt the CPU). Its tasks would include providing abstraction between RAM and every device that uses RAM, and providing...

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