At least for the initial version, one limitation on the hardware is going to be that for TPI, PDI and UPDI, the unused pins will not necessarily be quiescent. It's on the user to insure that the NC pins of the programming interface are actually not connected, or that unexpected signals on those pins won't do any harm. They will at least be confined to the target power voltage range, but for example, MOSI will have a copy of the transmit data on it and SCK will have a copy of the clock during PDI.
Also, target power will only be applied while programming takes place. If configured, target power will be applied and after a brief delay (perhaps 10 ms or so) the programming cycle will begin. When it's over, target power will be dropped.