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Wrapper rewrite

A project log for Libre Gates

A Libre VHDL framework for the static and dynamic analysis of mapped, gate-level circuits for FPGA and ASIC. Design For Test or nothing !

Yann Guidon / YGDESYann Guidon / YGDES 7 days ago0 Comments

Good news everyone !

The benchmarking results are encouraging and made possible thanks to a new, rewritten version of the wrapper, which now even handles some essential generics ! You can expose generics of integers and string-based types, including std_logic, text and SLVx.

The core of this tool relies on GHDL's XML output, which is then parsed by a crude bash script. This is part of the new release :-)

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