BTW I don't think C-gate is possible in VHDL level - at least not for FPGA where fully synchronous nature of the circuits is a must...

Almost anything is possible in VHDL, if you can write a logic diagram for it. There is a logic loop but one can coerce a synthesis tool to accept it (i've done this before).

LibreGates should be able to process loops too (provided a "meta gate" is included) because I need to handle asynch circuits for the Y8's debugger.

it might be closely tight to specific chip and virtually unportable to other chip families or even other chips of the same family - I'm familiar with such approach when workability of synthesized bitstream depends on order of modules listed and phase of the Moon - you adds something minor and design stops working forever :)

@SHAOS  gates are gates... I assemble them however I want :-)

Furthermore the asynchronous types are used only in certain parts of the debugging circuit of Y8. The portability issues are limited to only a tiny part of the system :-)

> gates are gates...

Will synthesizing tools optimize out some of your gates when convert your logical circuits to LUTs?

@SHAOS  Synthesis tools will detect and complain about "logic loops".

There is a trick however : at a certainly low description level, with LibreGates, the use of fundamental gates for the netlist might bypass some checks that are done at a higher logic level.

Synthesisers are not meant to remove fundamental gates, particularly if they are manually defined. Otherwise there must at least be an error or warning message and the synthesiser risks changing the behaviour of the circuit, since the synthesiser might not know exactly what the loop is meant for.

Logic loops should be kept very small, usually 2 or 3 gates long. If there is a trouble, the equivalent function could/should be turned into a macrogate or something like that, in case the synthesiser is really uncooperative. Longer asynch loops should be avoided, of course.

As for LUT, this is something quite specific and it requires tool-specific intervention. I had no trouble doing manual set/reset latches with Microsemi's Libero. Using manual insertion of fundamental gates, it was easy to solve.

What do you mean by "fundamental gates"?
Low level library components for specific FPGA?

@SHAOS  Yes,

this project started indeed as a replacement library for the A3P family, for which Actel has a whole catalog of "gates" that are recognised by the synthesiser and that map directly to the hardware.

My interest was in efficiency (speed, space) but without compromising the portability of my code, which could become trapped by their tools. So I wrote my own library, open sourced, derived from the public documentation. So I could write Open Source FPGA code that could always be used on other architectures. I can also use GHDL instead of the manufacturer's proprietary and limited toolset.

The rest if feature creep :-)

ok, then you need to try TinyTapeout or even directly apply to efabless' GP180 or SKY130 free shuttles to become "silicon proven" :)

I even did C-gate with hysteresis constructed out of discrete PMOS and NMOS transistors in my 1st chip in 2015 :)
And it was working pretty well ;)