A project log for Libre Gates

A Libre VHDL framework for the static and dynamic analysis of mapped, gate-level circuits for FPGA and ASIC. Design For Test or nothing !

yann-guidon-ygdesYann Guidon / YGDES 05/28/2023 at 23:010 Comments

More discussions and looking around later, it appears that Liberty files, created back in the 80s by Synospsys, contain a field that might be an afterthought but is critical for my purpose, and Liberty files are the standard way to exchange ASIC cell characteristics. Here is how one cell is described :

/* --------------- *
 * Design : AND2X1 *
 * --------------- */
cell (AND2X1) {
area : 72;
  cell_leakage_power : 0.12537;
  pin(A)  {
    direction : input;
    capacitance : 0.0181648;
    rise_capacitance : 0.0181286;
    fall_capacitance : 0.0181648;
  pin(B)  {
    direction : input;
    capacitance : 0.0178174;
    rise_capacitance : 0.0178174;
    fall_capacitance : 0.0176984;
  pin(Y)  {
    direction : output;
    capacitance : 0;
    rise_capacitance : 0;
    fall_capacitance : 0;
    max_capacitance : 0.497268;
    function : "(A B)";
    timing() {
      related_pin : "A";
      timing_sense : positive_unate;
      cell_rise(delay_template_5x5) {
        index_1 ("0.01, 0.025, 0.05, 0.15, 0.3");
        index_2 ("0.06, 0.18, 0.42, 0.6, 1.2");

This is from osu025_stdcells.lib (TSCM 0.25µ library). This open directory also provides the VHDL VITAL model, where the logic gates are described in great detail for the timing in particular. But that's not what I'm here for : I work at the earlier stages in the boolean domain. VITAL simulations will be useful later for detailed simulation, after all the fault injections have been dealt with.

Liberty is probably the most popular format for a SDK to provide timing characteristics. Most EDA prefer Verilog and as highlighted above, the gates contain the function, which I could extract. I could reenact my feat as I did with the custom XML parser (written in bash) but I have cold feet as the XML parser is only intended to read from one tool in particular, with a very specific format, while Liberty is used and generated by a wide variety of tools that I hope to interface with. I don't know yet what I am facing.

I only need to regenerate the basic gate function, so I just want inputs pins, output pin, and a boolean function between them. All the rest is then processed by LibreGates. Meanwhile I realise that my system (like so many others) only handles gates with one output.

There are some useful resources online, such as the Synopsys document for the format and a Python parser. Extracting the gate names, functions, pin names will not be too hard. However I need to make it work with the existing code so I consider using an intermediate file format that will make the VHDL generation easier and more modular. It will hopefully split the complexity between the Liberty filter and the VHDL metaprogramming mess.

One of the little issues I'll have to deal with is the description of the boolean equations of the Liberty format : AND has no operator sign...

The other issue will be with the sequential gates, as they are way more diverse than the boolean gates.

I think I have an idea for the intermediary format, using function calls to be directly executed and cut down the parsing requirements.