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TG68 Hardware

A project log for 68K CPU with Frame Buffer on FPGA

Working with AMR's build and improvements to the TG68 FPGA project

land-boardscomland-boards.com 09/06/2020 at 14:040 Comments

This project is intended to be a software project but a description of the hardware is necessary as a reference to understand the resources available to the software.

Features

FPGA Cards

Flow Status    Successful - Sun Sep 06 12:05:04 2020
Quartus Prime Version    20.1.0 Build 711 06/05/2020 SJ Lite Edition
Revision Name            SOC
Top-level Entity Name    C5BoardToplevel
Family                   Cyclone IV E
Device                   EP4CE15F23C8
Timing Models            Final
Total logic elements     7,984 / 15,408 ( 52 % )
Total registers          3629
Total pins               134 / 344 ( 39 % )
Total virtual pins       0
Total memory bits        107,520 / 516,096 ( 21 % )
Embedded Mult 9-bit els  2 / 112 ( 2 % )
Total PLLs               1 / 4 ( 25 % )

TG 68000 Core

32MB SDRAM

Host Serial Interface

Video Display Unit

Memory Map

Discussions