fpga risc-v soc

Simple implementation of risc-v soc on fpga

misha

Following Follow project

Liked Like project

Become a Hackaday.io member

Just one more thing

To make the experience fit your profile, pick a username and tell us what interests you.

OK, I'm done! Skip

Similar projects worth following

466 views

2 comments

3 followers

2 likes

View Gallery

Description

This repository contains an extremely simple implementation of the RV32I ISA
*Entirely written in Verilog.
*Every opcode need one clock cycle to execute, except memory operations(store/load).
*Used 1 port block ram ip for memory inteface
*Not designed with multiple RISC-V harts .
*The privileged ISA is not implemented.
*FENCE, FENCE.I and CSR instructions are not implemented.