This repository contains an extremely simple implementation of the RV32I ISA
*Entirely written in Verilog.
*Every opcode need one clock cycle to execute, except memory operations(store/load).
*Used 1 port block ram ip for memory inteface
*Not designed with multiple RISC-V harts .
*The privileged ISA is not implemented.
*FENCE, FENCE.I and CSR instructions are not implemented.
C compiled rom which is runing on risc-v core prints number between 0 to 15 on 7 segment display