LM5161 Based DC-DC Bias PS

4W, +5, +12 bias PS using TI's LM5161.

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SPECIFICATIONS (as configured)
+ Vin 10.6 - 30V DC (tested to 25V)
+ # Outputs - 2 (V1, V2)
+ V1 - +5V, 300mA, 1.5W, non-isolated
+ V2 - +12V, 200mA, 2.4W, [non]-isolated
+ Output ripple: V1 < 10mV P-P, V2 < 20mV P-P
+ Regulation: V1 - 1%, V2 - 11% (over Vin range, V1 & V2 @ full load)
+ Transient response (3mS pulse, 20%->100% load)
V1 - 250uS
V2 - 960mV droop
+ Peak efficiency: 84.5% (V_in=14V, V1 & V2 @ full load)
+ Average efficiency: 83% (over Vin range, V1 & V2 @ full load)
+ Low efficiency: 81.5% (Vin=10.6V, V1 & V2 @ full load)
+ Radiated EMI: not tested
+ Operating temperature: -40C (characterized) - +85C (tested)
+ Soft start
+ Protection: over current, thermal shutdown
+ Dimensions(LWH): 4.7cm x 2.3cm x 1.6cm (1.85" x 0.91" x 0.63")
+ Unit cost: $23.00 (excluding assembly time & materials)

I often need a DC-DC bias supply for my projects that supplies a few outputs, typically 5V & 12V, only a few watts, and most often non-isolated. There are a lot of COTS choices in this range with unit costs under $20.00 but I often find that they don't meet some key spec. Most often it is the dual output requirement combined with a Vin range from ~10V ~ 25V. In the past I've worked around this by going with a single 12V output followed by a 5V linear regulator. Not a big deal but it is more parts to source & place along with a bit more dissipation.

I've often kicked around the idea of designing one that has some configuration flexibility but I didn't want to spend the time (a 5W design can demand as much time as a 500W). Once more I find myself needing one for my Solar Charger and this time the itch got the better of me.

I had one of TI's LM5017 evaluation boards lying around and decided to give it a go. The attraction to the LM50xx family of regulators is their simplicity, small parts count, low cost, wide V_in range, and output configuration flexibility. They are non-isolated buck regulators but you can add additional windings to obtain additional outputs at different voltages. Those outputs can be isolated or tied to the primary ground. A constant on-time PWM scheme is used which eliminates the traditional compensation network required to close the control loop.

A quick characterization of the LM5017 showed that output ripple was a problem.

This is an artifact of the constant on-time control scheme: the control loop requires ripple for stability (a contributing factor is the small output capacitance).

Adding an small LC filter to the output solved this problem.

The LM5017's other problem is its current limit of 600mA which wouldn't be enough to handle power required of both outputs. No problem, the LM5161 is its higher power sibling that also integrates a few other features that the LM5017 requires discrete components for.

So, down the bunny hole I went.

The design was done in Kicad and the project is posted. It includes improvements from the article in the pictures. Also posted is my design workbook based on TI's datasheet guidance. Note that the as-built uses all MLCCs vs. electrolytics for output capacitance: this was done for space & cost and does not materially effect performance.

The logs provide additional detail on the design, build, and limitations: be sure to read them before you decide to build it. The design, inherent to the controller architecture, has problems:
+ Conditional stability
+ Secondary regulation
+ Current limit scheme

As long as these are understood it can be used successfully. I will likely use it in the prototype of my Solar Charger for a real-world test.

5V, 5W (1A) configuration.

Zip Archive - 48.94 kB - 03/07/2021 at 17:52



Design workbook with winding spec & BOM.

sheet - 33.11 kB - 11/13/2020 at 21:11


Kicad project files.

Zip Archive - 68.69 kB - 11/13/2020 at 21:11


  • 5V, 5W Version Posted

    Brian Cornell03/07/2021 at 18:05 0 comments

    I made a 5V, 5W buck derivative that is smaller than the flybuck design but uses the same input/output filter design for low noise/ripple applications. The inductor core is a Magnetics MPP C055048A2. with 38 turns of 24 AWG. Peak efficiency with a 12V input is ~ 89% at approximately 300mA load. Full load (1A) efficiency is ~ 82%. Lower largely due to DCR losses in the output inductor.

    The output voltage will drop ~ 230mV at full load due to these losses. Don't try to move the feedback sense to after the output LC: the phase shift is too great and will result in an unstable control loop (there is no sensible way to compensate with this controller). If tight regulation is required and the application can tolerate a bit more ripple the filter inductor can be removed. Alternatively you could go with an inductor that has a lower DCR but with the associated size/cost penalty.

    This design works with a 10-20V input but could easily handle higher input voltages. It includes a bias supply connection which is optional, even up to 20V (the controller uses an internal LDO when the bias supply is left open). Above 20V the bias supply should be used - refer to the data sheet for more information.

  • Main Inductor Characterization

    Brian Cornell11/14/2020 at 18:53 0 comments

    If you build this with the inductor spec in the project you can use this data to validate. The core is a Magnetics MPP #C055050A2, 125u permeability. Do not use any tape between windings: there is no creepage / clearance requirement since this is a non-isolated design and doing so will increase the leakage inductance.

    • V1 L=66uH
      • Tested @ 20V, 9uS pulse, V2 open
    • V1 leakage L=795nH
      • Tested @ 5V, 1uS pulse, V2 shorted
    • V2 L=458uH
      • Tested @ 20V, 25uS pulse, V1 open
    • V2 leakage L=5.3uH
      • Tested @ 5V, 1uS pulse, V1 shorted

    The test jig is a MOSFET driven by a function generator with a large bulk capacitor across the D-S connected to a bench supply. The current ramp is measured with a scope current probe (I use Tek's TCP202). The scope's cursors are used to measure the start/end of the current ramp and the actual rise time (will be longer than the function generator's pulse).

    From this the inductance is calculated: L=(V*dt)/di where:

    • V=supply voltage
    • dt=cursor measured rise time
    • di=cursor measured peak current

    Parasitic capacitance:

    • V1 Fr=1.8MHz, Cp=118pF
    • V2Fr=1.56MHz, CP=22pF

    This measurements were obtained using a function generator, two passive 1X scope probes, and a 4.7K resistor. One lead of the resistor is connected to a lead of the winding to be measured. The other resistor lead is connected to the function generator's positive lead. The generator's negative lead, along with the scope probe ground leads, are connected to the other lead of the winding. Connect one of the scope probes (say, CH1) to the resistor lead connected to the generator; connect the other probe to the resistors opposite lead (CH2). The other winding should be left open.

    Set the scope to trigger on CH1. Program the function generator for a 100kHz, 4V P-P sine wave (no DC offset) and increase in 100kHz increments until the CH2 signal reaches peak amplitude and is in phase with CH1. This is the self resonant frequency (Fr) of the winding. Calculate the parasitic capacitance:


    Where L is the measured inductance of the winding.

  • Limitations and Problems

    Brian Cornell11/13/2020 at 21:50 0 comments

    The old adage that "you get what you pay for" certainly applies here. A highly integrated solution with simple control schemes poses limitations that aren't easily fixed.

    Secondary regulation. The reasons for this have already been discussed and aren't a controller problem per se (any topology will exhibit) but one of coupling between the windings (i.e. leakage inductance). While a well built inductor will minimize this it won't achieve 1% (TI's demonstration boards using commercially built inductors are 10%). Hence, the secondary should be used to power circuits that can tolerate lose regulation.

    Conditional stability. This is a result of the complex interaction of V2's low impedance with the control loop and current limit scheme. It is similar to the right half-plane zero found flyback boost converters. The events I've observed to induce this are:

    1. Vin droops below UVLO and then recovers to some operating value within a few volts of Vin_min (drops that do not go below Vin_min to not induce)
    2. High capacitive load on V2

    Both happen when the secondary is loaded and the primary output is lightly loaded (~>20%) or open. The switching node will go from a stable pattern:

    To one of bursts followed by a long off-time:

    CH1 is the AC ripple component on the feedback (FB) pin which is necessary for stable operation.

    The secondary output voltage will drop to some fraction of its rated output but the primary voltage stays close to its regulated value. If a specific minimum load is applied to the primary, or the secondary load is removed & then reapplied, the controller will resume stable operation. This condition does not occur if both outputs are open or only the primary is loaded (any value). It also does not occur in the opposite direction (sudden increase in Vin).

    When the controller encounters these situations it begins by switching with minimum off-time (expected). After a few switching events, current has built-up in the inductor, trips the over-current circuit, and switching terminates. By this time the FB voltage is at or above Vref since V1 is not loaded. Several mS pass (I have measured +20) before the FB voltage drops below Vref and switching resumes. But energy in the secondary is gone so the process repeats. Crucial to this is the lack of synthetic ripple (AC component) on FB pin: it isn't generated due to the short off-times and already high voltage on the FB pin; it doesn't occur during 'cold starts' because the FB voltage is zero.

    There is no easy way to fix this. Decreasing R4 to increase the ripple feedback will reduce the V1 load threshold but will not eliminate the instability. A simple hack is to add a diode across the outputs to pull V2 down. A more complex one is to add a synthetic ripple (mabe just voltage sense?) circuit to the secondary and couple to the feedback pin with a resistive summing circuit. Both require a non-isolated secondary.

    I decided that the juice isn't worth the squeeze and instead tested the thresholds (Vin drop, minimum V1 load) necessary to avoid this condition (V1 load of ~ 60mA).

    Current limit scheme. This is a hazard and likely failure mode when V2 encounters a short or over-current condition with a high input voltage. The specific conditions are: secondary is under load and encounters a short, the primary can be loaded or open, and Vin is high (for my tests 25V).

    The controller uses a heuristic scheme to extend the off-time to limit the output current and provide a 'soft' foldback. A key determinant of the off time is the voltage at the feedback pin: the lower it is, the longer the off time. When the secondary shorts, the FB pin voltage remains close to its regulated value (2V) because the V1 output is fine (even when 100% load) and so the off time is short. The next switching cycle begins but is quickly terminated for over-current. The switching cycle looks like this:

    The high secondary current (<800mA - well beyond rated 200mA output), combined with the high Fsw sends...

    Read more »

  • Build

    Brian Cornell11/13/2020 at 21:41 0 comments

    Since one of my design requirements is flexibility, the PCB provides some customization without having to make a new board. That said, you can certainly incorporate this into a project and eliminate it as a disparate component.

    Secondary. The secondary can be isolated or tied to the primary ground. If an isolated secondary is desired R7 should be replaced with a 2.2nF MLCC reduce common mode noise.

    Controller bias. The controller has an internal linear regulator that is necessary for startup. Beyond startup, it is best to power the controller via one of the outputs if they exceed ~ 9V. As TI points out, high input voltages almost necessitate the use of bias to eliminate the dissipation from the internal regulator. Use a 603 size jumper to connect the appropriate output, and keep in mind that if the secondary is used it must be tied to common ground via a jumper at R7.

    Controller mounting. The controller has a thermal pad to improve heat dissipation. The PCB accommodates this and provides a generous copper pour. If you don't have a reflow oven or air pencil apply thermal paste instead. I used this method and the worst case rise was 50C.

    Main inductor build. The board is setup to use a toroid core with an OD of 13.5mm. As discussed in the Theory of Operation section, core selection & winding configuration are crucial to minimize leakage inductance. Ignoring core losses, a core with the highest permeability that provides an adequate saturation margin minimizes the number of turns. A high turns ratio complicates the build. If possible use a bifilar winding (1:1 ratios). Otherwise an interleave is best.

    For the inductor used in this project I used a simple interleave: winding 1/2 the secondary first, then the primary ('buck' winding), then the remaining secondary. Splitting the primary in half (so P/S/P/S) for four layers might get the leakage inductance a bit lower but it becomes difficult to do manually. The winding details are documented in the design workbook.

    Wire size, type, skin effect, etc. is a discussion unto itself but since the currents are relatively small here it is more just a question of wire AWG to minimize DCR balanced with the available winding window. Ideally the secondary would use 28AWG vs. 30 but the increase in leakage inductance isn't worth it: this happens because of the increased air gap between adjacent strands. The window utilization also becomes very high (a machine wound core with 28AWG secondary wouldn't be possible), making the winding sloppy and further degradating regulation.

    Installation. I intend to mount the unit as a daughter board using 20AWG wire with nylon spacers (hence, no mounting holes).

  • Theory of Operation

    Brian Cornell11/13/2020 at 21:40 0 comments

    TI's datasheet does a good job of explaining the controller architecture so I won't cover that. Additional guidance can be found in application notes AN-1481 & AN-2292. Instead I'll focus on those aspects specific to this implementation.

    Main inductor. I wound my own inductor on a Magnetics MPP core because I couldn't find anything off the shelf meeting my spec; if at all possible use a commercially built one (unless you are really good). The secondary winding is not regulated which makes it very sensitive to leakage inductance. In other words, output voltage regulation is dependent on this. This is the reason for the 11% V2 regulation spec. I only got this after three different cores and six winding configurations.

    If you do build your own inductor try to keep the turns ratio and overall # turns low. This spec uses a 2.6:1 ratio for the secondary which is a likely limit. A high number of turns / ratio increases leakage inductance. The winding build itself (layers, wire, etc.) also has a huge influence and this is discussed more in the <build> log.

    V2 snubber (C18, R8). These were added during evaluation to reduce the leakage inductance ring. This trace shows the unclamped ring.

    Although it did not appear to materially increase D2's dissipation I elected to add it for reduced EMI. Trace below is with snubber installed.

    At higher input voltages R8 will dissipate ~ 250mW.

    LC filters. The input and both outputs include LC filters to reduce ripple and switching spikes. The values for these were obtained empirically by observing the frequency spectrum in the outputs without filters and then calculating the minimum required inductance. A larger value was then selected based on size & saturation margin. Resulting worst-case AC ripple (CH1=V1, CH2=V2):

    Input capacitance is sized to minimize input current ripple and for convenience I used the same inductor to filter switching spikes.

View all 5 project logs

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