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LED Coupled Logic

A project log for LED Coupled Logic (LCL)

Reaching sub 1 ns propogation delay with LEDs and bipolar transistors.

TimTim 11/30/2020 at 22:480 Comments

I'll try to keep it brief. You have seen me investigate several different styles of discrete logic, including the weird DTL derivative LTL.

One obvious omission was emitter coupled logic, ECL.

A basic ECL inverter is shown above. The key is the long-tailed pair on the left side, which acts as a saturating differential amplifier. The emitter follower formed by Q4 is used as a voltage buffer and sets proper input logic levels. The non-input branch of the input pair is typically tied to a reference voltages which is in-between logic low and high levels. Since ECL does not drive the transitors in saturation, it can be extremely fast. Due to high static biasing it is also extremely power hungry, roughly 10 mA per gate. The Cray 1, one of the most famous supercomputers was entirely based on integrated ECL logic.

Let's ponder about the right side of the differential pair (Q3). It does not only consist of a resistor and transistor, we need a static bias reference in addition. This adds a lot of components to what could be a simple RTL or NMOS inverter.

But who says we have to form a differential pair from two identical transistors? The circuit above shows an inverter formed from an assymmetric differential pair consisting of a LED and a bipolar transitor. The benefit of this is that it saves one transitor, one resistor and the bias reference.

The plot above shows the input-output relationship of the inverter. The threshold level is at 3.0V, the high level is at 3.25V, while the low level is at 2.8V. The output voltages increases again if the input is driven far above Vh. This  behavior is similar to ECL.

To test the propagation delay, I simulated a simple 5 stage ring oscillator.

Oscillator frequency is 138.7 MHz, which means that the tpd is 720ps. There is some overshoot, which appears to increase voltage swing.

Just like for ECL and RTL, the basic gate for this logic style is a NOR gate. The output buffer allows combing the outputs of several gates to form a wired AND.



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