Single-board computer initial design & PCB

A project log for 6809 SBC

A 6809-based SBC with DES encryption hardware.

philmacphailPhil.macphail 12/31/2020 at 11:350 Comments

With a working cross-assembler and basic design, I am ready to design the board the preparation was intended for. The outline specifications are –

The detail implementation turned-out to be quite straightforward, with a couple of extra constraints to fit the ‘small steps’ approach. I knew there was a good chance of making errors in the design so I wanted to be able to implement the original one within the new one, which meant including a 6850 for early testing. Only the address of the chip changes, so if the monitor runs then I know I have both RAM and EEPROM working. From there I can use the monitor to check each feature in turn.

Memory Map

The peripherals are all mapped to a 2k address space between $F000 and $F7FF. After reset the rest of the upper 32k is mapped to the EEPROM when reading, and RAM when writing, but the EEPROM can be disabled to give 62k of RAM. The intention is that code in the EEPROM can be copied to RAM at the same address then the processor switches to RAM-only without any other functional change.

An extra twist is that a 4k segment between $E000 and $EFFF can be mapped to any 4k segment of RAM by writing to a single register.

There are enough complexities here to be a challenge to debug so I was reliant on the monitor and serial interface to get me started.


This is the design created, that I was hoping was mostly functional

Initial schematic


This is the PCB I received, before I assembled it