Functionality Explanation

The RTC is comprised of the 15-bit and 32-bit counters shown in Figure 1 and Figure 2. By analyzing the datasheet’s macrocell diagram in Figure 2, we can learn more about the configuration registers for this block as well as the associated matrix connections.

This block’s operation centers around the 32-bit time counter and the 32-bit alarm DCMP illustrated in Figure 2.The operation is simple: for every rising edge of its clock, the count value held within the time counter registers increments by one until it reaches 232-1. Upon reaching this value, the next clock signal causes the counter to “overflow” to zero and restart its count. When the registers of the time counter match the alarm DCMP registers, the “RTC DCMP Out” signal will go high. The RTC block operates in the 32-bit configuration as described above when the RTC’s 32-bit counter is clocked, through mux selection, by the “RTC Clock” matrix output. 

Please note that the RTC’s clock input should have an active high pulse width exceeding 1 µs. Assuming a 50% duty cycle, this specification allows for input clock frequencies that are less than or equal to 500 kHz. 

Looking back at Figure 2, we see the inclusion of another 15-bit counter within the RTC macrocell. This counter’s output, when selected by the mux as the 32-bit time counter’s clock, becomes the 15 least significant bits (LSBs) of a 47-bit counter configuration. The 15-bit counter overflows at 215-1 in the same way as previously described for the 32-bit counter.  When the 15-bit counter overflows to “0”, the 15-bit counter clocks the 32-bit counter and the RTC block outputs a “1” into the matrix through “RTC CNT DIV Out.” 

A key feature of the 15-bit counter is that it pairs well with a 32.768 kHz crystal oscillator. By selecting “32767” for the “Init. counter divider data” section of the RTC property window, the user can create 1-second pulses to clock the 32-bit time counter. This trivializes the process of creating arbitrary timing signals with the RTC block as you can simply calculate the desired delay in seconds and set the “Alarm DCMP value:” registers accordingly.

If you take another look at Figure 1 and Figure 2, you can see a matrix output named “SYNC” that connects to what we call the “Shadow Buffer.” This 48-bit buffer can be used to both read from and write to the 15-bit and 32-bit counters. Figure 3 shows the register contents for this shadow buffer which are located at the I2C addresses from 0x75 to 0x7A.

Register <989> controls the direction of the shadow buffer data transfer. When triggered by a rising edge of “SYNC,” a digital “1” configures the RTC block to load the counter registers with the data stored inside the shadow buffer. Alternatively, a digital “0” in register <989> stores the current count value of each of the counters in the shadow buffer registers. 

These register transfers are synchronized to one of two sources selected by register <990>: a rising edge on the “SYNC” matrix output as previously described or an I2C trigger signal. A digital “0” selects the “SYNC” trigger and vice versa. The I2C trigger signal is generated internally by reading (when register <989> is “0”) or writing (when register <989> is “1”) to any of the shadow buffer register addresses.  

The shadow register guarantees a stable I2C read from the RTC count registers when triggered via I2C. If you were to perform an I2C read on the counter registers directly, the register contents might increment during the read time, resulting in an incorrect I2C read. By copying the register contents into the shadow buffer, the GreenPAK™ allows the RTC counters to continue operating while the user reads the shadow...

Read more »