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Adria - A 65C816 based computer

Adria is a WDC65C816 based computer, inspired by RC2014.
Main goal is to create a DIY friendly computer

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This is my second attempt at creating a 65C816 based computer.

The first one, Lilith, was mostly for learning designing a computer and writing a ROM. It was a "Single Board Computer". But with the size of 300mm x 200mm, you couldn't call her small.

This one, Adria, is inspired by RC2014 and is modular. The CPU board, memory logic decoding board, RAMand ROM are all seperate boards, which connect to a backplane, using dual row right angle header pins.
Adria will have 4 peripheral slots.

Adria can be powered by a 7V to 25V power supply, the backplane has a LM7805 as voltage regulator.

Currently I have a 6551 (not the WDC65C51!) and a NXP SC28L92 UART board, which will be installed in slot #1.

System monitor is a (minimal) rewrite of Supermon816, mostly to have it assembled with the CC65 environment. The ROM will include an Intel Hex Uploader.

ROM source and KiCad project files should be published soon

Dimensions

Backplane162mm x 95mm
Peripheral boards95mm x 50 mm

Blank templates for the boards (in KiCad format) are available. These should be installed in the KiCad template directory (for your system)


Memory Decoding Logic

Memory decoding is done with two GALs (22V10, I used Atmel). This is the only "slot" with an additional 10-pin connector, which holds the /IOSEL signals and the /DEVSEL signal.

The equations are written for and compiled with PALASM.

/DEVSEL is not used (yet), but theoretical I can use this for selecting an on-card ROM?


Memory Map

The system was designed with a simple memory map. This is the momery map as it is right now. This might change (some compacting is needed)

$FFFF
$FFF0   |________Emulation mode interrupt vectors
$FFE0   |________Native mode interrupt vectors
$FD00   |________Reset routine(s)
$FCA0   |________Fixed jump table
$FC00   |________Interrupt Service Routine(s)
$D800   |________Supermon816 (adapted from original by BigDumbDinosaur)
$D000   |________Intel Hex Uploader (adapted from original by Ross Archer)       
$CD00   |________UART driver (inspired by and based on code by BigDumbDinosaur)
#C020   |________UART I/O registers (mapped to UART card using GAL)
$C000   |________
$BFFF   |
        |
$8000   |________Free RAM
$7FFF   |________Supermon816 stack
        |        (growing down...)
        |
        |
        |
$2200   |________Free RAM
$21FF   |
        |
$2180   |________UART Channel B TxD buffer
$217F   |
        |
$2100   |________UART Channel B RxD buffer
$20FF   |
        |
$2080   |________UART Channel A TxD buffer
$207F   |
        |
$2000   |________UART Channel A RxD buffer
$1FFF   |        
        |
$02E6   |________Free RAM
$02E4   |________Character scan routine vector
$02E2   |________Character input routine vector
        |        (Reserved)
$02DE   |________Software BRK vector
$02DC   |________Software BRK vector checksum
$02DA   |________Software INT/IRQ vector
$02D8   |________Software INT/IRQ vector checksum
$02D6   |________Software NMI vector
$02D4   |________Software NMI vector checksum
$02D2   |________Software Reset vector checksum
$02D0   |________Software Reset vector
$02EF   |
$0266   |________Free RAM
$0265   |
        |
$0246   |________(Supermon 816 auxbuffer)
$0245   |
        |
$0200   |________Keyboard buffer
$01FF   |
        |
$0100   |________Hardware stack
$00FF   |
        |
$0000   |________Zero Page

RAM

The board currently available is for an AS6C1008 SRAM. This should give the computer 128 kbyte of RAM


ROM

Two boards are designed,

  • A board for the 28C256 (32k x  8) variants EEPROM, currently only 16 kbyte is used.
  • A board for the 29F040 4 Mbit Flash (this has worked well in my previous design, Lilith)

UART

There are currently two options for UART:

  • A 6551 based board (not the WDC 65C51, because of hardware issue)
  • A NXP SC28L92 based board (has 2 UARTs, supports higher speeds)

  • Just have to reorder some memory

    Xander Maas03/18/2021 at 19:18 0 comments

    Running some tests/applications (e.g. ehBASIC) showed me, I have have to rethink my memory usage in bank $00. I will have to move the monitor stack higher up in memory, maybe start the stack at $BF00. Also I want to move the UART buffer(s) lower in memory. This will free some extra (continuous) memory I can use.

    The new memory map might look like this:

    $FFFF
    $FFF0   |________Emulation mode interrupt vectors
    $FFE0   |________Native mode interrupt vectors
    $FD00   |________Reset routine(s)
    $FCA0   |________Fixed jump table
    $FC00   |________Interrupt Service Routine(s)
    $D800   |________Supermon816 (adapted from original by BigDumbDinosaur)
    $D000   |________Intel Hex Uploader (adapted from original by Ross Archer)       
    $CD00   |________UART driver (inspired by and based on code by BigDumbDinosaur)
    $C020   |________UART I/O registers (mapped to UART card using GAL)
    $C000   |________Start of ROM
    $BFFF   |________Supermon816 stack
            |        (growing down...)
            |
    $A000   |________Bottom of stack (?), giving 8kByte of stack
    $9FFF   |________Top of free RAM
            |
            |        (Giving 37.5 kByte of free RAM)
            |
    $0A00   |________Free RAM
    $09FF   |
            |
    $0980   |________UART Channel B TxD buffer
    $097F   |
    $0900   |________UART Channel B RxD buffer
    $08FF   |
    $0880   |________UART Channel A TxD buffer
    $087F   |
    $0800   |________UART Channel A RxD buffer        
    $07FF   |
            |
    $02E6   |________Free RAM / RESERVED?
    $02E4   |________Character scan routine vector
    $02E2   |________Character input routine vector
            |        (Reserved)
    $02DE   |________Software BRK vector
    $02DC   |________Software BRK vector checksum
    $02DA   |________Software INT/IRQ vector
    $02D8   |________Software INT/IRQ vector checksum
    $02D6   |________Software NMI vector
    $02D4   |________Software NMI vector checksum
    $02D2   |________Software Reset vector checksum
    $02D0   |________Software Reset vector
    $02EF   |
    $0266   |________Free RAM
    $0265   |
            |
    $0246   |________(Supermon 816 auxbuffer)
    $0245   |
            |
    $0200   |________Keyboard buffer
    $01FF   |
            |
    $0100   |________Hardware stack
    $00FF   |
            |
    $0000   |________Zero Page
    

  • ehBASIC works

    Xander Maas03/08/2021 at 20:24 0 comments

    Completed my changes to the ehBASIC source (v2.22p5C) in order to run BASIC in Adria. The source, with my changes, will be available in my GitHub repository.

    Unfortunately ehBASIC is too large right now to be implemented in ROM. This means it has to be loaded everytime I want to play with BASIC.

    Also found a few little bugs in the Supermon816 source, these are now corrected.

  • Some housekeeping done...

    Xander Maas02/24/2021 at 16:39 0 comments

    Received the v2.0 version of the backplane. The backplane is now 4-layer, with ground and power planes as layer 2 and 3. I forgot to remove the ground-fill on the bottom layer, let's see how that works out.

    Also published the project files on GitHub and write down the memory map (as it is right now) in the project details.

  • Just a backlog of logs

    Xander Maas02/22/2021 at 20:22 0 comments

    The project has been started in december 2020. A first run of boards has already been done, as has a second run.

    In the meantime, I have updated the backplane to a 4-layer PCB, with ground and power (+5V) in the inner layers and signals routed at the top and bottom layers. These haven't arrived yet, but should in a few days. This new (4-layer) revision should make it possible for me to run the computer at higher clock speeds.

    Also the first run of the backplane had some "small" issues:

    • U3 missed the feedback from pin 8 to pin 12 (/PHI2) for the clock divider
    • Missed all /IRQ and /NMI traces to and from the CPU slot and all peripheral slots

    Also I have had a few 6551 (I used a SY6551) UART and NXP SC28L92 UART boards manufactured. With the help of some great people at forum.6502.org, I now have a working driver in ROM for the SC28L92, so the (speed) limited 6551 board isn't in use right now.

View all 4 project logs

  • 1
    Running ca65 to assemble the ROM

    First of all, you will need to have cc65 installed, which will depend on the OS you use. Please see the website of cc65 for more information.

    When you use Linux or macOS, I have made a Makefile, which may make life easier. Just run

    make default

    in the rom directory and you should get a bios.bin file (32 kbyte) which you can burn into a 28C256 (or equivalent).

    If you prefer to do it manually, see the commands in the next code snippet

    cl65 -t none -l bios.lst -o main.bin main.asm
    cp main.bin > bios.bin
    cat main.bin >> bios.bin

    I copy the rom twice into the final bios.bin file, as I have not (yet) found a way to burn a smaller binary at a specific offset with the Linux minipro command. 

  • 2
    Soldering the components

    I have included (or try to include) iBOM HTML pages for all boards, as to make it easier to find what to solder where

View all instructions

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