Just as I begin building the Turing machine part of this project, I get an insight in to how to better balance the bias voltages in the folded cascode input stage. After a quick recalculation of the voltages and currents, SPICE is reporting nearly 70dB gain at 60kHz. Oh my. I may need that AGC circuit, after all.

With the digital clocking logic built, I began to build the 'tape' part of the system. The plan was to use a 16 bit up/down counter to pluck a value from an SRAM chip. Nope, no 8 bit up/down counter chips on hand. Sadly, there is only one 4 bit up/down counter chip in the stash. (Even looked over some old mother boards.) Implement a counter with gates and flip-flops? Madness!

Since the result is derived from the input, would an EPROM be a solution? Each 8 bit value would require 2 values, one would be "up", the other "down". Using a 74x273 latch to hold the previous output of the EPROM, a new clock pulse to the latch would latch a new value based on the status of the up/down signal. This could work.