Early on, I chose quadrature clock to control the system. It would yield a 50% duty cycle, lots of useful timing states and, in a typical implementation, the complements of both timing signals. While I was working out the gating arrangements for the various latches, write lines, and other control signals, I noticed that state sequence of the clock was identical to that of a Johnson counter. Those are synchronous counters that can be implemented in a typical PLD, with plenty logic cells remaining for other uses.

Reducing the chip count on a protoboard is always welcome, add in some re-programmable logic (in case I goofed up DeMorganizing) and I see a win. There's one last chip that may be merged in to the GAL16V8 that I had in mind, a 74HCT00 that is mostly used as the clock oscillator. Can I make a GAL be its' own clock source?

The flip-flop in the output cell of the GAL-V chips can be bypassed, allowing an output to act as an ordinary logic device. Looking at a few oscillator schematics, most could be implemented with inverters or inverter and buffer combinations. After a trial, or two, it occurred to me to upgrade the inverter and buffer to XOR gates. Now I have selectable invert or non-inverting inputs for both devices, by simply moving a jumper to VCC or Gnd, respectively.

An appnote from OnSemi provided some useful insight in to building the oscillator. The first few attempts didn't work, but then one variation began to oscillate when I powered down the circuit. Some poking and prodding later... Oh, right gate input current. The gate input isn't the gate, it's the source terminal. Check the datasheet, the input leakage is up to 100uA, with a 0.8V logic threshold. Drop a 7.5k resistor in there, it starts up every time! The only rant is that the duty cycle is around 40%, but connecting the oscillator output to the clock input of the same GAL to drive the registered outputs of the counter will clean that up.

It is an odd looking thing, but it is a adjustable frequency oscillator and quadrature clock divider that uses just 4 cells of a PLD. I wasn't planning to make this a PLD centric project, they're just so handy.