One of the more interesting things to do with a hardware definition language is of course the simulation of logic. Due to hefty build times when targeting an FPGA, simulation is the major way to develop and refine HDL projects. So of course hdlpy has to have a simulator.
When modelling hardware you run into the subject of multi-value logic. Inevitably, because digital logic is more than just ones and zeroes: there's also high impedance signals and their interactions with other signals to model.
Thus I had to settle upon a multi-value logic system for hdlpy.