(work in progress...)
Is the design of a 68000 single board computer (SBC) difficult? If you see the huge chip (dip 64) you should think so, but it is relatively simple. Compared to other CPU's like the Intel 8086, the address and data-lines are all directly available. Boards with 8086 CPU needs several latches to demultiplex the address and databus, and extra chips means extra wires.
For a simple design you need to connect all the address-lines of the CPU to the address-lines of the ROM and RAM, dito with the datelines. Besides that, a couple of logic chips will complete the design.
In this chapter I explain how I designed the SBC; I hope this will inspire you to build a SBC also, wether is is 68000, 6502 or Z80!
The design had to be simple (KISS/keep it simple, stupid); a minimum of chips but "by the book". It should run a pascal compiler I was writing:
- 64/128K SRAM (that should be enough; DRAM is to complicated).
- EPROM for BIOS/start up, size doesn't matter.
- UART for simple but fast input/ouput (no VDI).
- VIA for timer interrupts and basic input/output.
- No bus-buffers.
- No keyboard / floppy disk / harddisk / sound / video card etc.
I read a couple of books and magazines I found about this subject and took what I liked.
The MC68000 cpu needs ROM at startup at address 0x0000 till 0x0007 for stack pointer initiation and program start address. On the other hand the (interrupt)vectors are located in the first 1 KB, which you like to be in RAM-memory. But hey, KISS we decided, so the ROMs are at 0x0000and the vectors are fixed!
A 74LS139 demultiplexer gives you 4 banks for ROM/RAM/IO. The popular 62256 SRAM's are 8 x 32K large so every bank has a size of 64K. (Remember that the data-bus is 16 bits wide, so you always need two ROM chips and two (or four) RAM-chips).
|0x0.0000 - 0x0.7FFF
0x0.0000 - 0x03FFF
|0x1.0000 - 0x1.FFFF
|0x2.0000 - 0x2.FFFF
|0x3.0000 - 0x3.001E
0x3.0001 - 0x3.0003
|VIA / IO
|16 bytes (even bytes)
2 bytes (odd bytes)
The good old and uncomplicated! 78S05 linear voltage regulator gives 1.5 Amp; more than enough for the system. Although this kind of regulators spoils a lot of energy, this is how it was done the 90's.
The CPU has two lines (/HALT and /RESET) which has to be asserted for at least 100 mSec at startup for a proper reset. A fine task for the good old 555. But the /HALT-line also is an output that signals the CPU is running. So it's better not to connect /HALT and /RESET together. That means extra glue logic (open collector inverters 74LS05) and a LED as run-indicator.
The CPU is running on 8MHz; to get a nice 50/50 duty cycle a divider is added, although I have seen many projects with no divider. Perhaps you can skip that part, but I used the other part of the 74LS92 also for the correct clock for the UART.
/DTACK & /VPA
The MC68000 can work asynchronous (/DTACK) and synchronous (/VPA). /DTACK is used for ROM and RAM; with this line you can add wait-states, which we don't want. (For a simple design it's better to lower the clock speed if the memory is to slow). /VPA is for MC6850 (UART) and MC6522(VIA) devices. Be aware the /DTACK and /VPA should not be asserted at the same time.
- /VPA should be low when reading/writing to the UART/VIA. It should also be low when the processor is performing an interrupt cycle. The processor expects a vector on the bus, but much easier is the initiate an auto vector. The interrupt cycle is active if /AS is low and FC0, FC1 and FC2 are all high. Luckily FC2 doesn't need to decoded.
- /DTACK should be low when reading/writing ROM and RAM, so simply invert the /VPA line.
The MC6850 has a programmable internal...Read more »