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Logic board interface

A project log for MS6205 graphical mode

Modifying the MS6205 (МС6205) display to control every pixel individually instead of sending text characters

leszek-jakubowskiLeszek Jakubowski 05/24/2021 at 15:390 Comments

Edit: I had KSI1 and KSI2 mixed up. I fixed the pin and graph descriptions.

After connecting an oscilloscope to the different pins of the logic PCB-anode PCB interface I think I've got enough info to work on driving every connected pixel.

The pins are as follows:

  1.  +240В (+240V)
  2.  АСИЧ (ASICh) - anode clock 2 (for even anodes)
  3. АСИН (ASIN) - anode clock 1 (for odd anodes)
  4. КСИ2 (KSI2) - cathode clock 2 (only signal going from anode driver PCB to logic driver PCB)
  5. КСИ1 (KSI1) - cathode clock 1
  6. Х1 (H1) - lowest bit of cathode selection number
  7. Х3
  8. Х2
  9. Х6
  10. Х7 (H7) - highest bit of cathode selection number
  11. Х5
  12. Х4
  13. Гр. А2, А4, А6 (Gr. A2, A4, A6) - even anodes serial data
  14. +5В (+5V)
  15. Гр. А1, А3, А5, А7 (Gr. A1, A3, A5, A7) - odd anodes serial data
  16. Общий - Ground

The clocks for loading anode data work at a 3:4 ratio since every character is 7 lines high and there are 4 odd and 3 even pixels to load. The loading is split to speed up the whole process.

an oscilloscope diagram showing 3 pulses and an empty space equal to 1 pulse cycle, measurements of the whole pulse cycle with approximately 50% fill read 2.4µs and 416.6kHz
Pin 2 - 1 clock tick missing after every 3 ticks
an oscilloscope diagram showing a series of uninterrupted pulses, measurements of the whole pulse cycle with approximately 50% fill read 2.4µs and 416.6kHz
Pin 3 - all 4 ticks present

The clocks are going at about 416kHz, but the exact timing is not critical. The clock source is a RC stabilized oscillator done on 4 XOR gates of D20 (bottom of logical board schematic. As long as the shift registers, RAM, ROM and address generation logic can keep up the clock signal is valid.

Next up is the Cathode clock pulses by the monostable trigger on the anode driver side from a square wave into very short pulses. It's sent back to the logic board on KSI2 (cathode clock 2) as a "ready for another vertical line" signal. This is the only signal going backwards.

oscilloscope diagram showing 2 spike pulses, measurement between the 2 spikes read 95.6µs and 10.46kHz
Pin 4 - pulse spacing
oscilloscope diagram a zoomed in pulse with diagonal rise and fall, measurements show 150ns pulse width
Pin 4 - pulse shape measurements
oscilloscope diagram, another zoomed in pulse with more vertical rise and fall, measurements show 100ns pulse width
Pin 4 - pulse shape measurements

The square pulse, which is sent after all the Anode data is shifted into the registers and the right number is set on H1-H7 to select the loaded vertical line and latch the data from the anode shift registers into outputs. Triggers latch on falling edge. It's  just a square blip on KSI1 (cathode clock 1).

oscilloscope diagram, a series of square pulses, approximately 25% fill, measurements from one pulse to another shows 96µs and 10.42kHz
Pin 5 - pulse spacing
oscilloscope diagram, a series of square pulses, approximately 25% fill, measurements of the pulse width shows 19µs
Pin 5 - pulse shape

KSI2 and ¬KSI2 are more interesting on the anode driver PCB, where they control the latching of both the H1-H7 cathode selection number and the anode shift registers into the actual high voltage outputs.

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