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OpenCores PDP-8 on FPGA

OpenCores PDP-8 on FPGA

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OpenCores PDP-8 on FPGA with Front Panel on a QMTECH EP4CE15 FPGA on top of my RETRO-EP4CE15 Card

Got it up and running with my PDP-8 Front Panel in a couple of days. Runs OS/8. Added a built-in ANSI terminal from Multicomp.

From OpenCores PDP-8 page:

Features

PDP-8 CPU

In this FPGA implementation, the PDP-8 CPU can be configured to emulate the instruction execution of a PDP-8 (Straight-8), PDP-8/S, PDP-8/S, PDP-8/I, PDP-8/L, PDP-8/E/F/M, PDP-8/A, HD-6100, or a HD-6120.

The CPU does not attempt to emulate the execution of any particular PDP-8 implementation. The clock rate is different, the number of clock cycles per instruction is different, and the bus implementation is different. The default is a PDP-8/A.

Just for fun, the CPU incorporates a single cycle multiplier and a single cycle barrel shifter (currently disabled).

MS8C 32K-Word Memory

The system includes 32K-Words of memory. Unlike normal RAM memory, the FPGA memory can be initialized at power-up. The memory is in this system is initialized as follows:

  • RK8E Bootstrap program at location 0023
  • BIN Loader at location 7626 (07627 ?)
  • RIM Loader at 7756.

You can initialize the memory to all zeros if you are old-school and feel the need to use the front panel to toggle-in the boot loaders.

KC8E Front Panel

This device provides an interface to the front panel switches and LEDs that were present on the PDP-8/E front panel.

My PDP-8 Front Panel is supported in my build.

KE8 Extended Arithmetic Element

The PDP-8 Extended Arithmetic Element (EAE) provides optional advanced mathematics capabilities. The EAE is used to perform 23-bit floating-point and 24-bit integer operations. The EAE provides 24-bit add, subtract, load, store, multiply, divide, normalize, increment, complement, shift, and rotate instructions.

The KE8 EAE can be disabled.

KM8E Extended Memory

The basic PDP-8 architecture provided a 4K-word address space. The KM8E provides a memory extension mechanism that allows the PDP-8 address 32K-words of memory. The memory is all internal to the EP4CE15 FPGA.

The KM8E Extended Memory can be disabled.

KM8E Time Sharing

The KM8E time-sharing mechanism allows the CPU to operate in either Executive Mode or User Mode. In User Mode, instructions that could effect the operation of another program generate a User Mode Interrupt so that the operating system can handle the instruction correctly.

The KM8E Time Sharing can be disabled.

DK8EA/DK8EA/DK8EP Real Time Clock

The Real Time Clock (RTC) is used to create periodic interrupts to the processor. The RTC can be configured to operate in the following modes:

  • 1 Hz (DK8-EC)
  • 50 Hz (DK8-EC)
  • 100 Hz (DK8-EA as if 50 Hz primary power is applied)
  • 120 Hz (DK8-EA as if 60 Hz primary power is applied)
  • 500 Hz (DK8-EC)
  • 5 KHz (DK8-EC)
  • Var (DK8-EP)
  • Var (DK8-ES)

All timing is generated from the on-board 50 MHz crystal oscillator

KL8E Asynchronous Serial Interface

The system provides two serial interfaces.

LS8E Printer Interface

The LS8E device provides an interface to a serial printer. The device can provide hardware handshaking or XON/XOFF handshaking with the printer without software support.

PR8E Paper Tape Reader

The PR8E device provides an interface to a serial paper tape reader such as the Decitek 760. The device can provide hardware handshaking or XON/XOFF handshaking with the paper tape reader without software support.

KL8E Disk Controller

The Disk Controller is designed to 'front end' a Secure Digital disk chip which behaves as if it were four RK05 Disk Drives. The disk format is the same as SIMH so all of the SIMH disk images may be reused without change. 

Runs OS/8 from SD card.

  • Speeding Up the IOP16 CPU

    land-boards.com07/03/2021 at 20:47 0 comments

    The IOP16 runs at 8 of 50 MHz clocks per instruction. That is 6.25 MIPS which really is way more than fast enough for this use. The states are Grey Coded as follows:

    Most of the cycles do nothing. There is no good reason this can't run twice as fast. The Grey Codes are:

    Made the change and it worked. It now runs at 12.5 MIPS. Way overkill, but why not.

  • Fixed PS/2 Backspace Key

    land-boards.com07/03/2021 at 14:09 0 comments

    The backspace key that the PDP-8 expects isn't the CTRL-H key (0x08 ASCII value) . The key needs to be mapped to ASCII 0x7F. Fortunately, the PS/2 keyboard VHDL code (ps2_keyboard_to_ascii.vhd) makes this easy to change. 

    It works!

  • Auto-detect Serial Source

    land-boards.com07/03/2021 at 13:33 0 comments

    It's a great retro feeling to use the amber VDU screen and PS/2 keyboard built into the FPGA. However, sometimes I prefer to use PuTTY on the USB serial terminal, particularly when I want to capture screens. But the use of the serial source jumper does present the possibility of confusion to which port is being used (VDU or USB serial).

    Added auto-detection of the Serial port source. If the serSelect jumper (J3-1) is installed the USB is used. The serSelect is routed to the IOP16 CPU and checked. If USB is selected, the VDU screen shows "USB" added to the banner. This is useful to let the user know that the VDU is not being used.

    Output on PuTTY:

  • Improved ANSI Screen

    land-boards.com07/02/2021 at 09:49 0 comments

    Added subroutines for UART and VDU initialization to the IOP16 code. Also, added an ANSI screen clear command (0x0c). Here's a handy ANSI codes chart.  

    Here's the IOP16 code (latest version is here).

    000    START   0xA017    JSR    INITVDU         INITIALIZE THE VDU    
    001            0xA01C    JSR    INITURT         INITIALIZE THE ACIA UART    
    002            0xA014    JSR    CLRSCR          CLEAR THE SCREEN CMD    
    003    LOOP    0xA006    JSR    KB2PDP          KEYBOARD TO PDP-8    
    004            0xA00D    JSR    PDP2VDU         PDP-8 TO VGA    
    005            0xE003    JMP    LOOP            LOOP FOREVER    
    006    KB2PDP  0x6004    IOR    Reg0    IO_04   READ KBD STATUS    
    007            0x8001    ARI    Reg0    0X01    MASK RX DATA PRESENT BIT    
    008            0xC004    BEZ    NOKDBD          NO KBD DATA    
    009            0x6105    IOR    Reg1    IO_05   READ KBD DATA    
    00a            0x9180    ORI    Reg1    0X80    MARK PARITY    
    00b            0x7101    IOW    Reg1    IO_01   WRITE TO UART DATA    
    00c    NOKDBD  0xB000    RTS                    DONE KEYBOARD TO UART    
    00d    PDP2VDU 0x6000    IOR    Reg0    IO_00   PDP-11 TO VDU    
    00e            0x8001    ARI    Reg0    0X01    MASK RX DATA PRESENT BIT    
    00f            0xC004    BEZ    NOPDPD          NO UART DATA    
    010            0x6101    IOR    Reg1    IO_01   READ UART DATA    
    011            0x817F    ARI    Reg1    0X7F    8 TO 7 BITS    
    012            0x7103    IOW    Reg1    IO_03   WRITE OUT SCREEN    
    013    NOPDPD  0xB000    RTS            DONE    UART TO VGA    
    014    CLRSCR  0x200C    LRI    Reg0    0X0C    SCREEN CLEAR    
    015            0x7003    IOW    Reg0    IO_03   WRITE OUT SCREEN    
    016            0xB000    RTS                            
    017    INITVDU 0x2003    LRI    Reg0    0X03    RESET TERMINAL COMMAND    
    018            0x7002    IOW    Reg0    IO_02   WRITE VDU CMD REG    
    019            0x2020    LRI    Reg0    0X20    TX CTRLS RTS    
    01a            0x7002    IOW    Reg0    IO_02   WRITE VDU CMD REG    
    01b            0xB000    RTS                            
    01c    INITURT 0x2003    LRI    Reg0    0X03    RESET UART COMMAND    
    01d            0x7000    IOW    Reg0    IO_00   WRITE UART CMD REG    
    01e            0x2020    LRI    Reg0    0X20    TX CTRLS RTS    
    01f            0x7000    IOW    Reg0    IO_00   WRITE UART CMD REG    
    020            0xB000    RTS                            
    

  • Built in ANSI Terminal

    land-boards.com07/02/2021 at 00:16 1 comment

    There was enough resources to put my ANSI Terminal into the FPGA. It displays on a VGA monitor and input comes from a PS/2 keyboard. The ANSI Terminal uses my IOP16 CPU. The terminal connects via an internal 9600 baud serial connection.

    The IOP16 code is pretty simple. The only "tricky" part is adding MARK parity when sending serial data to the PDP-8 serial in and stripping off the MARK parity when sending the data out of the PDP-8 into the VDU. 

    000            0x2003    LRI    Reg0    0X03    RESET TERMINAL COMMAND    
    001            0x7002    IOW    Reg0    IO_02   WRITE VDU CMD REG    
    002            0x2003    LRI    Reg0    0X03    RESET UART COMMAND    
    003            0x7000    IOW    Reg0    IO_00   WRITE UART CMD REG    
    004            0x2020    LRI    Reg0    0X20    TX CTRLS RTS    
    005            0x7002    IOW    Reg0    IO_02   WRITE VDU CMD REG    
    006            0x2020    LRI    Reg0    0X20    TX CTRLS RTS    
    007            0x7000    IOW    Reg0    IO_00   WRITE UART CMD REG    
    008   START    0xA00B    JSR    KB2PDP          KEYBOARD TO PDP-8    
    009            0xA012    JSR    PDP2VDU         PDP-8 TO VGA    
    00a            0xE008    JMP    START           LOOP FOREVER    
    00b   KB2PDP   0x6004    IOR    Reg0    IO_04   READ KBD STATUS    
    00c            0x8001    ARI    Reg0    0X01    MASK RX DATA PRESENT BIT    
    00d            0xC004    BEZ    NOKDBD          NO KBD DATA    
    00e            0x6005    IOR    Reg0    IO_05   READ KBD DATA    
    00f            0x9080    ORI    Reg0    0X80    MARK PARITY    
    010            0x7001    IOW    Reg0    IO_01   WRITE TO UART DATA    
    011   NOKDBD   0xB000    RTS                    DONE KEYBOARD TO UART    
    012   PDP2VDU  0x6000    IOR    Reg0    IO_00   PDP-11 TO VDU    
    013            0x8001    ARI    Reg0    0X01    MASK RX DATA PRESENT BIT    
    014            0xC004    BEZ    NOPDPD          NO UART DATA    
    015            0x6001    IOR    Reg0    IO_01   READ UART DATA    
    016            0x807F    ARI    Reg0    0X7F    8 TO 7 BITS    
    017            0x7003    IOW    Reg0    IO_03   WRITE OUT SCREEN    
    018   NOPDPD   0xB000    RTS                    DONE UART TO VGA    
    

    Resources

    GitHub repo is here.

    It worked!

  • FPGA Resources

    land-boards.com05/30/2021 at 19:36 0 comments

    Uses most of the internal SRAM. Plenty of logic space left over:

  • Enabled Hardware Handshake on TTY1

    land-boards.com05/30/2021 at 19:32 0 comments

    Thought it might be a useful idea to have hardware handshake enabled.

    In the top file CPU entity:

         -- TTY1 Interfaces
         tty1BR   => uartBR9600,                 --! TTY1 is 9600 Baud
         tty1HS   => uartHShw,                   --! TTY1 uses hardware handshake
         tty1CTS  => TTY1_CTS,                   --! TTY1 CTS (in)
         tty1RTS  => TTY1_RTS,                   --! TTY1 RTS (out)
         tty1RXD  => TTY1_RXD,                   --! TTY1 RXD (to RS-232 interface)
         tty1TXD  => TTY1_TXD,                   --! TTY1 TXD (to RS-232 interface)
    

    From Doug Jones PDP-8 page. "From the beginning, PDP-8 software has generally assumed that textual I/O would be in 7 bit ASCII. Most early PDP-8 systems used teletypes as console terminals; as sold by DEC, these were configured for mark parity, so most older software assumes 7 bit ASCII, upper case only, with the 8th bit set to 1. "

    In PuTTY:

    Works!

  • Running OS/8

    land-boards.com05/30/2021 at 18:13 0 comments

    Fresh Boot

    • USB cable disconnected (FPGA card is off).
    • Run/Halt on Front Panel set to HALT (down position).
    • Set Address switches on Front Panel to 0023.
    • Plug in USB cable to PC.
    • PC LED on Front Panel should display next address (0024).
    • Run PuTTY on PC.
    • Serial port found in device Manager.
    • Serial port set to 9600,SPACE,7,1 (may not be optimal but it worked).

    • Turn on RUN switch on Front Panel.
    • Press RES button on Front Panel.
    • Prompt comes up in Serial terminal (PuTTY).

    Reboot

    The Internal SRAM needs to reloaded.

    • Run/Halt on Front Panel to HALT (down position).
    • Hit load switch on FPGA card (SW3).
    • Turn on RUN switch on Front Panel.
    • Press RES button on Front Panel.
    • Prompt comes up in Serial terminal (PuTTY).

    Alternate Re-boot

    From the OS8 Handbook. Boots to command line.

    • Set Run/Halt to HALT
    • Set switches to 7600
    • Press RES (Reset)
    • Press LDPC (Load PC)
    • Press RES (Reset)
    • Set Run/Halt to RUN
    • Press RES

    Files on the RK08 (SD Card)

    • DIR /A
    ABSLDR.SV   6            FLOP2 .BI   2            RALF  .SV  19
    ADVENT.DC   9            FORLIB.RL 170            REMEM .SV   5
    ADVENT.FT  11            FOTP  .SV   8            RESORC.SV  14
    ADVENT.IN   1            FRTS  .SV  26            RKBOOT.SV   2
    ADVENT.LD 145            FUGUE .MU  42            RKCOPY.SV  11
    ADVENT.RL   4            FUTIL .SV  27            RKFRMT.SV   9
    ADVENT.TX 201            F4    .SV  20            RKUTIL.SV  15
    AINDX .DA  50            GETIN .FT   6            RLFRMT.SV   7
    AMAIN .RA 270            GETIN .RL   4            RL2FMT.SV   8
    AMAIN .RL  50            GETWRD.RA  16            RND   .FT   1
    ATEXT .DA 144            GETWRD.RL   2            RND   .RL   2
    A5TOA1.RA   6            HEADER.SV  14            RSPEAK.RA   3
    A5TOA1.RL   3            HELP  .HL 102            RSPEAK.RL   2
    BASIC .AF   4            HELP  .SV   8            RSTRGM.FT  13
    BASIC .BA  11            INIT  .TX   1            RSTRGM.RL   8
    BASIC .FF   4            INITAD.FT  65            RTFLOP.SV  15
    BASIC .OV  16            INITAD.RL  23            RUNAD .BI   1
    BASIC .SF   4            INUSE .TE   8            RXCOPY.SV   9
    BASIC .SV  11            IO    .FT   2            RXFIX .SV   3
    BASIC .UF   2            IO    .RL   2            RXREAD.SV   7
    BASIC .WS   1            JUGGLE.RA   3            SAVEGM.FT  13
    BATCH .SV  10            JUGGLE.RL   2            SAVEGM.RL   8
    BCOMP .SV  17            KL8E  .PA  53            SD    .BN   1
    BITMAP.SV   5            K12DEB.SV   4            SD    .LS  28
    BITSET.RA  11            K12DEC.SV   5            SD    .PA  11
    BITSET.RL   3            K12DJG.SV  33            SEED  .RA   7
    BLOAD .SV   8            K12ENB.SV   4            SEED  .RL   2
    BLOCKS.SV   8            K12ENC.SV   6            SET   .SV  20
    BOOK  .BI   1            K12MIT.SV  33            SPACWR.BA  39
    BOOT  .SV   5            LAYOUT.TX   4            SPEAK .RA  28
    BRTS  .SV  15            LCSYS .BI   3            SPEAK .RL   4
    BUG   .FT   3            LOAD  .BI   1            SRCCOM.SV   5
    BUG   .RL   2            LOAD  .LS   8            SVDUMP.SV   4
    BUILD .SV  37            LOAD  .SV  16            TDCOPY.SV   7
    CAMP  .SV  13            LPTSPL.SV  10            TDFRMT.SV   9
    CARRY .RA   5            MCPIP .SV  13            TECKBM.TE   2
    CARRY .RL   2            MOVE  .RA   4            TECO  .IN   1
    CCL   .SV  31            MOVE  .RL   2            TECO  .SV  32
    CHESS .SV  15            MSBAT .SV  23            TECO  .TE   1
    COMPAF.SV   5            MUSIC .SV   9            UCSYS .BI   3
    COMPIL.BI   2            PAL8  .SV  19            USR   .RA  46
    CONVRT.SV   5            PARAM .SV  12            USR   .RL   4
    CREF  .SV  13            PASS2 .SV  20            VOCAB .RA   7
    DECX8 .SV  43            PASS2O.SV   5            VOCAB .RL   3
    DIRECT.SV   7            PASS3 .SV   8            VTEDIT.TE   8
    DOUGTE.ST   1            PCT   .RA   2            WILD  .BI   1
    DROP  .RA   4            PCT   .RL   2            WILD  .DI   5
    DROP  .RL   2            PIP   .SV  11            WILD  .TE   2
    DSTROY.RA   1            PIP10 .SV  17            WILD  .TM   1
    DSTROY.RL   2            PSPEAK.RA   5            WPFLOP.SV  14
    DTCOPY.SV   5            PSPEAK.RL   2            YES   .FT   2
    DTFRMT.SV   7            PUT   .RA   3            YES   .RL   3
    EDIT  .SV  10            PUT   .RL   2            2000  .TX   1
    EPIC  .SV  14            QUIT  .SV   2            31    .76   1
    FLOP  .HN   3
    

     Resources

    .R RESORC
    */E
    
    163 FILES IN 2639 BLOCKS USING 5 SEGMENTS
    553 FREE BLOCKS (7 EMPTIES)
    
    #  NAME TYPE MODE SIZ BLK KIND U V ENT USER
    01 SYS  RK8E RWF 3248 SYS      0 F  07
    02 DSK  RK8E RWF 3248 SYS      0 F  07
    03 BAT  BAT  R        16         B  00
    04 TTY  TTY  RW       17+ KL8E   E 176
    05 RKA0 RK8E RWF 3248 20  RK05 0 A  20
    06 RKB0 RK8E RWF 3248 20  RK05 0 A  21
    07 RKA1 RK8E RWF 3248 20  RK05 1 A  22
    10 RKB1 RK8E RWF 3248 20  RK05 1 A  23
    11 RKA2 RK8E RWF 3248 20  RK05 2 A  24
    12 RKB2 RK8E RWF 3248 20  RK05 2 A  25
    13 RXA0 RX02 RWF  988 21+           32
    14 RXA1 RX02 RWF  988 21+           36
    15 B3    37  RWF      22+          117
    16 B4    37  RWF      22+          113
    
    FREE DEVICE SLOTS: 01,  FREE BLOCK SLOTS: 03
    OS/8 V3T
    

  • Creating SD Card

    land-boards.com05/30/2021 at 18:04 0 comments

    Running VirtualBox under Windoze. Transferring files between Windoze and Linux via GitHub.

    Combined the 4 images inspired by Startup page:  

    Created single image.

    Burned to blank SD card using Balena Etcher.

  • Boot OS/8 from SD Card

    land-boards.com05/30/2021 at 17:13 0 comments

    OS/8 Boots:

    Set serial port configuration:

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