Some thoughts about using DDS with a PLL to achieve higher frequencies

A project log for ATtiny12L Selectable Frequency Generator

A low-power selectable frequency generator

scottScott 02/06/2017 at 08:321 Comment

Some thoughts about using DDS with a PLL to achieve higher frequencies

I’ve worked with DDS generators in the past. One such use was with an AVR microcontroller, specifically, an ATmega168 running at 10 MHz .

In that particular project, I wanted to be able to generate frequencies that were higher than those that the AVR could generate on its own using DDS. The DDS sampling frequency was limited to <50 KHz because the sampling rate was 100 KHz. Using the Nyquist Theorem yielded approximately a stable 50 KHz waveform with a slight jitter due to the fact that the DDS generator used a timer interrupt to signal the DDS algorithm to update the internal 24-bit DDS registers. In practice, there was up to 5 clock cycles of jitter. The DDS output is a square wave and the resulting output is also a square wave.

Because I wanted to generate frequencies in the 300 to 500 KHz and 1 to 2 MHz ranges, I decided that a frequency multiplier would best serve that purpose. To that end, I came up with a method that employed the use of a PLL, of which the CD74HC7046A was a perfect candidate because it was low-power and would operate down to 2 volts and the power supply ran at 3 volts.

In the implementation, I wanted to be able to select a range of frequencies for the two different bands. The VCO would not cover the full range of 300 KHz to 2 MHz, so by using an output on the AVR, I was able to shunt a resistor in parallel with another to achieve selection of the two different bands of frequencies. A partial schematic is shown below.

screenshot-pllPLL used as a frequency multiplier

Referring to the schematic above, leaving the AVR’s I/O pin set as an input essentially tri-stated the pin and thus had little effect on the fixed (and permanent) current mirror set resistor (R6), which enabled the VCO to run at the lower frequency range. Setting the I/O pin to a low output switched in the 2nd resistor (R5) in parallel to the first (R6), thus setting the VCO to oscillate in the higher frequency range.

The PLL needs a divider in the feedback loop to set the multiplier ratio. I realized that one of the 8-bit timers in the AVR could be used as a programmable divider, thereby creating a programmable multiplier. The formula for the divider ratio is (2 * (OCR[x] + 1)).

In the above circuit, DDSOUT is the DDS frequency generated by the AVR. TIMER0 was used as the divider. DIVIN goes to TIMER0’s input pin (T0), which is used as the clock source for the timer. DIVOUT is the OC0A ouput. An OCRA setting of “0” yielded a divide by 2, which translated to a 2x multiplier of the DDS signal. An OCRA setting of “1” yielded a divide by 4, which translated to a 4x multiplier of the DDS signal. BANDSEL is used to select the upper or lower bands of the VCO. The PLLEN signal was used to disable the PLL output so that frequencies in the 1 Hz to 50 KHz range could be directly generated by the AVR’s DDS output.

screenshot-mux-driverMUX and output driver stage

Referring to the schematic excerpt on the right, a single NC7SP157 ‘HC157 MUX (U8) was used to switch between the direct DDS and multiplied DDS outputs, which fed a complementary MOSFET output driver circuit comprised of Q1 and Q2. VPP is adjustable and sets the driver’s output level. In the actual circuit, VPP was driven by a MAX5026 boost-regulator, whose voltage setting resistor was via a MAX5463 programmable digital potentiometer under AVR control.


bcampbell01 wrote 10/17/2018 at 19:37 point

Thank you Scott !  You obviously put a great deal of effort into this and the related postings.  And I, for one, greatly appreciate it!   I get the sense that this whole area is about to gain a lot of interest ...if it isn't suppressed and the masses understand, from history, whom labels of "quackery" served - hint : it wasn't Humanity.

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