This project describes three PWM design variants using Dialog Semiconductor’s GreenPAK IC:

1. “0-100% PWM” is PWM signal generator with the possibility to control the signal’s duty cycle from 0 to 100% full range, controlled by external or internal signal (for instance: signal from external pin, I2C signal, from a comparator, etc.). 

2. “Programmable Limits PWM” is modification of “0-100% PWM” with settable maximum and minimum limits of the PWM’s duty cycle. The limits can be changed by I2C.

3. “Sawtooth modulated” is a PWM generator with settable maximum and minimum limits of PWM’s duty cycle and generates a sawtooth PWM modulation.

Below we described steps needed to understand how the programmable limits PWM have been programmed. However, if you just want to get the result of programming, download GreenPAK software to view the already completed GreenPAK Design File. Plug the GreenPAK Development Kit to your computer and hit the program to design the device.

How it works?

Let’s start from a simplified design. The following design is just a PWM generator that controls the PWM duty cycle with UP and DOWN buttons. 

The PWM’s duty cycle is determined by the shift between CNT3 and CNT5 output pulses. CNT3 counter data should equal CNT5 counter data. DFF3 is set by the rising edge of CNT5 pulse and reset by the low pulse of CNT3. CNT3 output is inverted, so active signal is LOW (see Figure 2).

To change the value of the PWM duty cycle we need to add one clock to CNT5 (to increase PWM duty cycle) or to CNT3 (to decrease PWM duty cycle). It can be done by external buttons to change the delay between the CNT3, CNT5 outputs. One clock makes 1 step shift (where 1 step shift = (1/(CNT5(or CNT3) counter data + 1)) * 100%). DFF2 and DFF4 are used to avoid an additional clock which can appear when a button generates a logic LOW. 

Figure 3 shows the design where a PWM duty cycle changes linearly. Also, there is a possibility to control the rate of the duty cycle change and control the direction of this change.

Here, CNT1 generates a clock signal. When “UP/DOWN_CTRL” pin is HIGH, the signal goes to CNT5 CLK input through 3-bit LUT2 (duty cycle increase). When “UP/DOWN_CTRL” pin is LOW, the signal goes to CNT3 CLK input through 3-bit LUT4 (duty cycle decrease).

2-L3 is just a buffer. This one is used to guarantee 0% duty cycle. In some cases, the design will work with 0% duty cycle without the 2-L3 buffer. However, if the propagation time of CNT5 is less than CNT3, it causes short pulses to appear at the output. So 2-L3 ensures a clean output when the duty cycle should be 0%. 

The rate of change of PWM’s duty cycle depends on the period of CNT1. PWM full ramp time from 0% to 100% duty cycle can be calculated using following formula: 

T_PWM_RAMP = CNT5 Counter Data * CNT1 Period

A part of the “0-100% PWM” design has been described above. This is a linearly changeable PWM, where the duty cycle is changed from 0 to 100%, controlled by an external signal. The rate of duty cycle change can be changed via I2C.

The button “HOLD” is for holding the duty cycle constant. This button just resets CNT1. CNT1 is reset by a HIGH level signal and keeps the output HIGH. 

The button “Reset to LOW” is used to reset duty cycle to 0%. 

DFF4 and DFF6 provide the upper limit of duty cycle to avoid overflow. These two DFFs measure the shift between two signals, the outputs of CNT3 and CNT5. When the shift is equal to 1.5 clock period of OSC0, these DFFs detect it and reset CNT1. Thus, the duty cycle doesn't change while UP/DOWN_CTRL signal stays HIGH. When CNT1 is reset, its output goes HIGH, generating one more clock signal and RC OSC signal isn’t inverted anymore by 3-bit LUT2. You can see it in Figure 7 and Figure 8. When the shift becomes 1.5 clock period, Maximum duty cycle at output of...