A 16-bit RISC CPU with 32 instructions built with Digital and verilog for an FPGA.

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This is a CPU built from scratch in a visual way using a digital circuit simulator called Digital. This is then able to be exported to verilog or VHDL and that can be converted into a digital circuit that can run on an FPGA.

It also has a retro-style graphics system, modeled after late 80s Video Display Processors (VDP / VDU) and game consoles.

All this is recorded in a series of youtube videos showing my progress.

This is a CPU built from scratch in a visual way using a digital circuit simulator called Digital.

This is designed to be a 16-bit RISC Minimal Instruction Set Computer with a limit of 32 instructions (or really, 32 opcodes), and is meant to run in a ICE40 FPGA using open source tools.

All this has been recorded on youtube showing my progress. The first few episodes are pretty amateur, but I get better as the series goes on. I start off trying to teach some concepts, but later on transition into more build videos with commentary. 

There is also a video display circuit designed to work with DVI over HDMI with a PMOD.

The circuit is a retro Video Display Processor (VDP), sometimes also known as a Video Display Unit (VDU), or Picture Processing Unit (PPU). It's designed to work similarily to a late 80s graphics system like in the Commodore 64 / Amiga, or the various Nintendo or Sega consoles of that era.

It uses an 8x8 tile based system, with a 40x12 text display of 16x32 pixel characters, of which are made of tiles with 3 shades plus transparent available in 16 colours. The resolution is 640x400 with a 12bpp colour depth.

Currently this is hard-coded to display the frontpanel blinkenlights, but the text is now in a framebuffer so that could allow CPU access to it soon.

Here is a playlist just of the videos showing how this part was built:

  • [005] Program Memory!

    rj4507/12/2021 at 22:56 0 comments

    Jan 14, 2021

    In this video I build out the program memory store from an EEPROM and build a simple programming interface for it. I also add a diagnostic output for the one instruction currently supported. This is to support building out more instructions very soon.

    As always, the video is available here:

  • [004] Register File!

    rj4507/12/2021 at 22:45 0 comments

    Jan 11, 2021

    In this video I build out the register file, and upgrade the instructions to allow specifying a source register and destination register for the add. The CPU has grown to this:

    The decoder is updated to this:

    And here's the new Register File module:

    And here's the video:

  • [003] Adding Multiple Numbers

    rj4507/12/2021 at 22:23 0 comments

    Jan 5, 2021

    Computers can do a lot more than just add two numbers. Let's figure out how to add multiple sets of numbers!

    I introduce multiplexers, a program counter, a demultiplexer, d-flip-flops (aka registers) and encounter a timing glitch!

    Here's what the CPU looks like after this episode:

    And here's the video:

  • [002] Humble Beginning Adding Numbers

    rj4507/12/2021 at 22:07 0 comments

    Jan 3, 2021

    Well, you gotta start somewhere, right?

    This video is mostly introducing some of the basics of Digital. I introduce how wires work, some of the components, embedded circuits (modules), etc. Eventually I get the beginnings of a decode and execute unit going. You can see the execute unit above, and the other units are just wires really. Here's a high level diagram:

    And here's the decode unit:

    Pretty humble.

    If you'd like to see this in video form and get the tutorial, you can watch that here:

  • [001] Introduction

    rj4507/12/2021 at 21:48 0 comments

    Jan 2, 2021

    At this point I have been building rj16 and recording videos of it. rj16 is a pipelined 16-bit 5 stage RISC processor, built in Go (golang). It had 127 instructions planned and was largely inspired by the SH-2 and M*Core processors. It was a grandiose design of epic proportions.

    But I realized allowing rampant feature creep was not the way to finish a project. Plus I got a craving to maybe one day build this CPU in discrete logic chips on PCBs. If I wanted to ever have any hope of that, I needed to scale down.

    I also wanted to build an OS for this processor, and at the time I was having difficulty finding anything that could fit in 64 KB (an issue I have since resolved). So I decided 32-bits would be easier for that goal.

    So, because all I had of rj16 was a simulator in Go, I decided to start from scratch building rj32, a 32-bit version of the processor. This would internally be a 16-bit processor (like the m68k), but with a 32-bit instruction set, and all operations would happen on pairs of 16-bit registers.

    And this time I decided to actually publish the videos on youtube for the first time. I had been recording for a while but too chicken to actually put those videos out there. But I decided that needed to change.

    So with that rj32 was born.

    I decided to build it in Digital with the intention of having it run on an FPGA, and keep it simple enough that maybe one day I could implement it with discrete 7400 series logic chips. And the whole journey would be recorded on youtube. Here is the very first video:

    Note: This was remastered after a couple weeks to be more concise and more appropriately represent the series as a whole

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