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[004] Register File!

A project log for rj32

A 16-bit RISC CPU with 32 instructions built with Digital and verilog for an FPGA.

rj45rj45 07/12/2021 at 22:450 Comments

Jan 11, 2021

In this video I build out the register file, and upgrade the instructions to allow specifying a source register and destination register for the add. The CPU has grown to this:

The decoder is updated to this:

And here's the new Register File module:

And here's the video:

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