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VHDL/Verilog to Discrete Logic Flow

Work in progress: Flow to synthesize VHDL/Verilog code into a PCB

TimTim
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The availability of cheap PCB manufacturing and assembly services seems to have sparked a renewed interest in designing digital circuits and processer from discrete transistor based logic. Now, why not go a step further and automate this process?

The final goal is to take VHDL/Verilog source and to turn this into design files (Gerber, P&P, BOM) that allow to manufacturing this design on a PCB.

There is nothing like building actual hardware from your design. FPGAs are a bit boring, ASICs still too expensive, so why not go discrete?

The Flow Architecture

Github repository: https://github.com/cpldcpu/PCBFlow


  • More Logic Family Validation

    Tim01/02/2022 at 14:52 0 comments

    Catching up on an additional round of synthesis test - from last year. I already implemented some changes after observing issues, so this is just an intermediate step.

    I combined counter implementation in four different logic families into one board of efficiency.

    1. RTL_2369: Resistor transistor logic with PMBT2369 and RL=RB=1kOhm
    2. RTPG_2369: RTL+Pass Gate Logic with PMBT2369 and RL=RB=1kOhm
    3. RTPG_3904: RTL+Pass Gate Logic with PMBT3904 and RL=RB=1kOhm
    4. Hybrid_3904: NMOS+Pass Gate Logic with 2N7002 and PMBT3904, RL=RB=1kOhm
    Read more »

  • Analog Multiplexer Logic - Second Attempt

    Tim12/06/2021 at 22:17 0 comments

    Next try at analog multiplexer logic: In addition to fixing the bug in the latch, I also added a few optimizations to the logic style: DFF are now taking only 4 amux and I introduced a few additional gate types (ANDN2, ORN2) that helped to reduced logic complexity. As a result, the counter now only takes 21 amux ICs, instead of 26 before. Furthermore, decoupling capacitors are automotically inserted now.

    Pure AMUX logic

    Read more »

  • Analog Multiplexer Logic and post layout extraction

    Tim11/21/2021 at 00:21 0 comments

    The flow is, of course, not limited to resistor-transistor-logik. In the meantime, I implemented analog multiplexer logic and already received a first PCB with the counter implemented in that logic style. The generated PCB is shown below. The analog multiplexers (BL1551) come in a tiny SC70 package and leave ample space for routing. The implementation of logic gates with multiplexers is quite efficient, hence only 26 devices are needed.

    Read more »

  • Hardware Verification

    Tim11/17/2021 at 23:47 0 comments

    The fully assembled PCBs arrived a bit quicker than expected. Time for some testing.

    Read more »

  • Getting Actual Hardware Made

    Tim11/09/2021 at 19:58 0 comments

    At some point everything has to be put to practice. So, today was time to order some assembled PCBs to check whether the flow actually results in working circuits.

    Read more »

  • 3 Transistor Latch -> 7 Transistor DFF

    Tim11/09/2021 at 19:43 2 comments

    One issue of the logic style I am using currently is that a D-Flipflop takes up no less than 15 units cells, 15 transistors, 30 resistors. This has a huge impact on design size and it would be great to do something about it.

    Months ago, I had a nice discussion with Yann on the TTLer HaD chat and we were competing in trying to reduce the number of transistors in a latch as much as possible. One amazing contraption that came out of this is the design below, that would certainly deserve a more detailed treatment than I can offer here.

    Read more »

  • Footprint Generation - PCBPlace.py

    Tim11/06/2021 at 23:44 0 comments

    After having figuring out where the cells are supposed to go, we need to figure out how to turn them into actual components on a PCB and write them out in a format that can be interpreted by a PCB design tool. As always, I spent most of the time looking for "shortcuts" and only started implementation then.

    Read more »

  • Placement - PCBPlace.py

    Tim11/05/2021 at 21:37 0 comments

    Finally coming to the tricky part - the placement. The purpose of the placement step is to assign physical locations on the PCB to every unit cell that was generated during synthesis. Cells cannot just be placed randomly, their placement has to be optimized according to various creteria.

    Read more »

  • Logic Implementation and Analog Simulation

    Tim11/03/2021 at 20:32 7 comments

    Basic logic gate implementation

    The synthesis step transforms the digital circuit into a spice netlist based on logic cells. To complete the circuit and allow analog simulation we have to actually implement the logic on devices level.

    Read more »

  • Synthesis and Technology Mapping

    Tim11/03/2021 at 19:04 2 comments

    This is where things get a bit more interesting. I was concerned that it was quite difficult to coerce Yosys into using my custom gate libraries, but in fact it was rather easy.

    The "cmos" example proved to be an excellent blueprint to creating a custom library. My logic family of choice is Resistor-Transistor-Logic (RTL), which is based only on resistors and transistors. Coincidentally, this is the same logic family that is used in the famous CDC6600 supercomputer. The basic logic element of RT-Logic is a NOR gate. Hence our design has to be implemented using inverters and NOR gates only. In addition, a storage element, a D-Flipflop, is needed.

    Read more »

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Discussions

victor.ezekiel wrote 10/24/2022 at 13:02 point

This is awesome. However, there is something I cannot seem to figure out. How did you convert the splice net-list to a schematic that can be used to generate the routing and 3d board.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 11/17/2021 at 21:14 point

Your page https://hackaday.io/project/180839-vhdlverilog-to-discrete-logic-flow/log/200258-3-transistor-latch-7-transistor-dff is gone, was this circuit a failure ?

  Are you sure? yes | no

Tim wrote 11/17/2021 at 21:48 point

I accidentally saved it as a draft. The 3T Latch works perfectly.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 11/17/2021 at 22:07 point

phew !!! I was worried :-D

One reason to worry is that certain bipolar transistors exhibit avalanche when reverse-biased, sometimes at quite low voltage, like 2V or less, which makes them unsuitable as pass transistors.

Testing the AF240

More characterisation

I tested old Ge transistors that behave this way, then the behaviour disappeared with more modern Si parts, but the latest RF/microwave transistors might have some reverse breakdown in the "unusable range" again as they trade speed for robustness.

I'm eager to read your report on this story !

  Are you sure? yes | no

Tim wrote 11/19/2021 at 22:47 point

Yeah, HF transistors are usually pretty sensitive to higher voltage. Especially Ge ones. Luckily the MMBT3904 is rather robust and appears to work in reverse operation as well, although at lower hfe.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 11/17/2021 at 14:57 point

If you can do a DFF (in 7 transistors ?), you can do a shift register and a Johnson counter. From there, you can do ser/des (UART ?) and counting/clockwork.

A clock would be the first thing one does with that technology, right ?

  Are you sure? yes | no

Tim wrote 11/17/2021 at 19:13 point

Sure, anything can be synthesized.

  Are you sure? yes | no

joan lluch wrote 08/21/2021 at 08:02 point

Wow, that looks to me as a very challenging and difficult project. It would definitely be extraordinary if you eventually figure it out !

  Are you sure? yes | no

Tim wrote 08/21/2021 at 09:04 point

It turns out that the part VHDL -> spice netlist of RTL logic  was actually comparatively easy and doable with Yosys. I have some scripts that do that automatically now.

I have been ponderings for a while about the best approach for place and route - e.g. abuse some of the FPGA tools out there (NextPNR, Verilog to Routing / VTR) or base it on an actual IC flow (OpenLane). Currently it looks like the latter is more accomodating, but the existing opensource tools are really archaic.

  Are you sure? yes | no

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