The availability of cheap PCB manufacturing and assembly services seems to have sparked a renewed interest in designing digital circuits and processer from discrete transistor based logic. Now, why not go a step further and automate this process?
The final goal is to take VHDL/Verilog source and to turn this into design files (Gerber, P&P, BOM) that allow to manufacturing this design on a PCB.
There is nothing like building actual hardware from your design. FPGAs are a bit boring, ASICs still too expensive, so why not go discrete?
To cut a (quite) long story short, you can see the flow I came up with below.
The input file is blue, the three output files are green. The red colored artifacts are technology description files. Intermediate files are grey.
I use GHDL/Yosys for synthesis and technology mapping. Unfortunately there was no obvious way to reuse some of the available free placement&routing tools, so I ended up implementing my own placement tool in Python - which is still in a very early state. As intermediate PCB format I chose the Eagle format, as this can be handled suprisingly easy in Python.The routing is done in Eagle (for very small designs) or Freerouting (for slightly larger designs). After routing I use EasyEDA for PCB outline addition, DRC and manufacturing file generation.
More details on implementation, examples and further progress in the next logs...
Automatic synthesis of digital circuits has been the domain of very expensive electronic design automation tools in the past decades. Since a few years, there seems to be considerable momentum to develop and make available free toolchains for ASICs and FPGAs.
Yosys is probably the project that started the renewed momentum in free EDA tools. Is a versatile framework for logic synthesis and initially targeted a verilog to FPGA flow with a backend specific to lattice FPGAs. In the mean time this has been extended to SymbiFlow an open source toolchain supporting many FPGAs. ghdl-yosys-plugin is a plugin based on GHDL that brings VHDL support to Yosys. (So I can achieve my goal of being able to use VHDL).
Is a verilog to FPGA toolchain with a freely configurable backend allowing to explore different FPGA architectures, which is in contrast to Yosys which is somewhat hardcoded for specfic FPGA architectures. It is based on a different logic synthesis tool, Odin II.
I pondered for a while whether it was possible to adapt a FPGA toolchain to create PCB based designs. The idea would be to provide a matrix of fixed functional elements and let the toolchain do the routing. Unused elements could be removed later. In the end I did not pursue this route since the toolchains are heavily geared towards working with larger functional elements (e.g. LUTs), which cannot be easily implemented in discrete logic on a PCB.
Qflow is an open source synthesis flow targeting integrated circuits, that combines several preexisting tools to a full workflow. It is available from http://opencircuitdesign.com/. Yosys or Odin II is used for synthesis, Greywolf for placement and routing, qrouter for routing.
The OpenLane flow is another digital design flow that picked up a lot of momentum and sees a lot of activity. It uses Yosys as the synthesis frontend and a newley developed tools, OpenROAD app, for placement and routing. The flow supports the /skywater-pdk, an open process development kit for a 130 nm CMOS process.
The problem of synthesizing digital logic for a PCB is actually very simular to synthesizing logic for an integrated circuit.
The image above shows the architecture of the OpenLane Flow (taken from here). The input to the flow is a our design file and a description of the technology, the PDK. At each step in the flow, the design is transformed in some way and saved in an internal representation until finally a layout file is generated. There are some feedback loops were tools parameters have to be finetuned to optimize the result.
Let's go through it step-by-step. Normal text is the OpenLane flow, italics are my thoughts.
yosys - Performs RTL synthesis
abc - Performs technology mapping
OpenSTA - Performs static timing analysis on the resulting netlist to generate timing reports
This step takes the Verilog/VHDL source and turns it into a list of logic gates. The critical step here will be to define a set of logic gates that can be implemented in discrete logic and convince the tool to map to only these gates. Timing analysis is a step we will skip for now as the focus should be to get a functional circuit at first. Improvement of maximum clock speed could be a later optimization.
Floorplan and PDN
init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
ioplacer - Places the macro input and output ports
pdn - Generates the power distribution network
tapcell - Inserts welltap and decap cells in the floorplan
The floorplan prepares the area where the synthesized logic goes and creates the power network. As a first step I will treat the power network as a normal net, which should be acceptable if performance is not a goal. A big question is wether the tools can be repurposed...
As stated in the introduction, the goal of this project is to create a workflow to generate a PCB with discrete (transistor based) logic from a hardware description language file. This should happen in a reproducible and automated way, with as little user interaction as possible.
Let's get one thing out of the way first, the inevitable question of "why"? Some possible reasons:
I'd like to use this as an opportunity to tinker with open source electronic design automation (EDA) flows and learn more about their inner workings.
The availability of low cost PCB manufacturing and assembly services had the side effect of allowing manufacturing of complicated discrete logic circuits for little money. Nothing more satisfying than to get actual hardware from your design.
More and more open source EDA tools are becoming available, providing a solid foundation to build on.
Because I (possibly) can! Well...
To be a bit more specific about the goals:
The source language should be VHDL, because that is what I am used to. Verilog is a close second, in case there is no other choice.
The target logic family should be resistor transistor logic (RTL). The reason for that is that the MMBT3904, a bipolar NPN transistor, is currently the cheapest transistor at the JLCPCB assembly service. I may also look into NMOS logic.
As a first step, the main goal should be to get a functional circuit that implements the HDL input. It is acceptable to compromise on performance. For example, timing analysis, clock tree insertion and power routing can all be introduced or optimized at a later time.