Goal Setting

A project log for VHDL/Verilog to Discrete Logic Flow

Work in progress: Flow to synthesize VHDL/Verilog code into a PCB

TimTim 10/04/2021 at 19:500 Comments

As stated in the introduction, the goal of this project is to create a workflow to generate a PCB with discrete (transistor based) logic from a hardware description language file. This should happen in a reproducible and automated way, with as little user interaction as possible.

Let's get one thing out of the way first, the inevitable question of "why"? Some possible reasons:

To be a bit more specific about the goals: