Optimizing for precision and speed

DMA

PDO reads should really be handled by DMA. Let us configure it and see how it goes. It works an then stops, it either randomly disconnects or starts to spew trash values, causing CiA402 state machine errors. Without DMA everything was working and was stable, so it is not power issue. Time to connect logic analyzer to see what is happening. At hand is cheapo FX2 based probe, to make it keep up SPI clock prescaler needs to be bigger, to drop clock frequency from max 41 MHz, to 5.125MHz. At this speed, transmission with DMA is stable back again. What can it be?

Turns out, simple SPI implementation (sending byte by byte) adds significant breaks between each byte. DMA sends all bytes in one go, back to back. SPI addressing can be done in 2 bytes, or 3 bytes (with wait state byte) - second solution is meant to give ESC enough time to fetch valid data from memory into SPI, but there is minimal cycle time value, Tread for that. According to datashet Tread should be at least 240 ns. Using 3 byte addressing with wait state should solve it, and it does, up to 21 MHz. Unfortunately at SPI1 max speed, 41Mhz, with current setup problem persists. Maybe it is caused by current board layout and it could be fixed on next HW revision? Then again, it looks to be fast enough to work on STMBL, and SPI2 on ODrive tops out on 21 MHz anyway so for now it looks good enough - on to next problems.

AX58100 moving towards interrupt mode - PDI interrupt and DC synchronization

It took a bit but now is working too. One needs to adjust settings in TwinCAT: assign Sync Unit to local device

Result is stable sync signal with very low jitter: about 150 ns even in large EtherCAT networks, according to Beckhoff claims

[TODO] oscilloscope shot of SYNC0 signals

Benchmark results

Despite slower SPI clock speed, cycle time is much better than LAN9252:

Polling (blocking SPI). SPI1 at 42 MHz

• Cables connected, ECAT master not connected: [ESC benchmark] 0006 us (0006 top)
• ECAT master connected, slv in OP: [ESC benchmark] 0015 us (0059 top)
• ECAT master connected, slv in OP, network startup hiscore reset: [ESC benchmark] 0015 us (0024 top)

Added CiA402 loopback, SPI1 at 42 MHz:

• ECAT master connected, slv in OP, network startup hiscore reset: [ESC benchmark] 0017 us (0025 top)

DMA SPI + CiA402 loopback. Prescaler 2 (42 MHz), SPI reads from ESC are unstable - transmission errors

• ECAT master connected, slv in OP: [ESC benchmark] 0017 us (0063 top)
• ECAT master connected, slv in OP, network startup hiscore reset: [ESC benchmark] 0017 us (0025 top)

DMA SPI + CiA402 loopback. Prescaler 4 (21 MHz: 2x slower clock), 2 us slower

• Cables connected, ECAT master not connected: [ESC benchmark] 0009 us (0009 top)
• ECAT master connected, slv in OP: [ESC benchmark] 0019 us (0073 top)
• ECAT master connected, slv in OP, network startup hiscore reset: [ESC benchmark] 0019 us (0030 top)

Seems like all that extra work with laying out another HW revision, and switching to new ESC from relatively unknown company, paid out. For now I will continue with AX58100. If anyone feels like stepping up and optimizing LAN9252 driver, PRs are welcome.