SpeakHDL is an Easy to Use FPGA Design Entry Tool:

SpeakHDL is a FPGA design entry tool focused primarily on ease of use and FPGA rapid prototyping. The novel approach of SpeakHDL is that it utilizes both procedural programming techniques and user voice commands to increase FPGA design productivity. 

A Quick Demo:

The video shown below is a quick demonstration on how a user would design a state machine with SpeakHDL. The example also shows the conciseness of the procedural programming approach and how closely the VHDL code maps to a graphical specification.

When the user says the "ok" voice command, SpeakHDL performs some background calculations, then automatically generates a testbench file, a top level file, and a user definitions file. These auto-generated files in addition to the API library is everything that needed to simulate and synthesize the design. Using the Xilinx Vivado Simulator,  we can see that our design simulates to what is expected.

Procedural programming for FPGA development is somewhat of a novelty in itself, however most of the ease of use comes from the fact that our "source code" is just natural language.  We could give the voice commands below to any user who wanted to re-create the example.

SpeakHDL Uses a Novel FPGA Design Pattern:

Under the hood, SpeakHDL utilizes our own Fixed Port Flat Architecture Design Pattern implemented in VHDL as a FPGA design strategy. So in a sense, it's the underlying design pattern that does all the work. However, the design pattern can be somewhat tedious and error-prone when coding it up by hand. SpeakHDL provides the usability piece that is missing from the design pattern.  It is a way to use voice commands to enforce some VHDL design rules and a uniform coding structure without imposing a huge learning curve on the user.

The Fixed Port Flat Architecture Design Pattern gets its name from the fact that every application module that uses the design pattern will have the same (7) signals at the port interface. 

              clk                        : in std_logic;
              reset                    : in std_logic;
              sm_input             : in std_logic_vector(-1 downto 0);
              sm_output           : out std_logic_vector(-1 downto 0);
              sm_io                  : inout std_logic_vector(-1 downto 0);
              next_state_rec   : out nsr_array (0 to 0);
              state_reg_rec    : in srr_array (0 to 0)

The port widths will be different, but the signaling will be the same.

The design pattern also makes use of a conceptually flat design architecture.  It is the flat architecture and the introduction of a shared framework module that makes procedural programming useful for FPGA design.

Application modules, (like the one we coded up with voice commands in our demo) behave like clients to a shared framework module, and it is the framework module that actually implements the procedure calls in hardware.

From a software prospective, the Fixed Port Flat Architecture Design Pattern can be considered a type of facade pattern that uses an abstract state machine as the facade object.  Two of the (7)  fixed port signals act to mask the complexity of the FPGA design and also decouple the application modules from each other.  

              next_state_rec   : out nsr_array (0 to 0);

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