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par2ser - a novel UART trasmitter

A project log for Intel HEX file input/output for FPGAs

Uploading / downloading Intel HEX file stream, implemented without embedded processor!

zpekiczpekic 7 days ago0 Comments

Refer to the UART basics, and the component source

When it comes to converting parallel data to serial format, an idea of shift register comes to mind, and this is how often such circuits are implemented. However, with start / stop / parity bits, the shift register must be longer than the data, and with parallel data already buffered, the number of register bits doubles.

This component uses a simple MUX instead, and a 4-bit counter (bitSel). Operation is as follows:

  1. Reset clears bitSel
  2. if bitSel is 0000, the clock input is MUXed to "send" input signal
  3. external circuit presents data at the input and on rising edge of "send":
    1. bitSel is incremented to 0001
    2. char is loaded from data (input data is free to change after this)
  4. now that bitSel is != 0000, the clock is MUXed to baudrate
  5. as bitSel is incremented with baudrate frequency, the 16-to-1 MUX presents the right output to TXD (1, 1, 1, 0, char(0)... char(7)...)
  6. after char(7), the next bit depends on parity mode if selected
  7. finally a stop bit is transferred to TXD (this is simply MUX input driven to '1')
  8. when bitCnt reaches 1110, it is reset to 0000 and the circuit is ready from step 2 above

When bitCnt = 0000, it can also be used as a ready signal for the higher level circuit, meaning par2ser is idle and waiting to be loaded with data to transmit.


Main clock is baudrate * 1, which is the speed at which TXD MUX needs to change inputs. The operation mode is given by 3 mode bits:

modedata lengthparityframe length
0XX8none10
1008space (0)11
1018mark (1)11
1108even11
1118odd11

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